;ELC ;;; Compiled ;;; in Emacs version 29.4 ;;; with all optimizations. #@27 VHDL Mode version number. (defconst vhdl-version "3.38.5" (#$ . 83))#@39 VHDL Mode time stamp for last update. (defconst vhdl-time-stamp "2015-03-12" (#$ . 157)) (byte-code "\301W\203\3021\303\304!0\210\202\210\303\305!\210\301\207" [emacs-major-version 25 (file-missing) require cl-lib cl] 2)#@42 Non-nil if GNU Emacs >= 22, ... is used. (defconst vhdl-emacs-22 (byte-code "\301X\205\302\207" [emacs-major-version 22 t] 2) (#$ . 390))#@110 Set variables as in `custom-set-default' and call FUNCTIONS afterwards. (fn VARIABLE VALUE &rest FUNCTIONS) (defalias 'vhdl-custom-set #[642 "\300\301!\203\301\"\210\202\302\"\210\211\205)\300@!\203\"\211@ \210\211A\262\202\207" [fboundp custom-set-default set-default] 6 (#$ . 537)])#@106 Check that the value of WIDGET is a valid directory entry (i.e. ends with '/' or is empty). (fn WIDGET) (defalias 'vhdl-widget-directory-validate #[257 "\300!\301\302\"?\205\303\304\305#\210\207" [widget-value string-match "^\\(\\|.*/\\)$" widget-put :error "Invalid directory entry: must end with `/'"] 6 (#$ . 843)]) (defconst vhdl-name-doc-string "\n\nFROM REGEXP is a regular expression matching the original name:\n \".*\" matches the entire string\n \"\\(...\\)\" matches a substring\nTO STRING specifies the string to be inserted as new name:\n \"\\&\" means substitute entire matched text\n \"\\N\" means substitute what matched the Nth \"\\(...\\)\"\nExamples:\n \".*\" \"\\&\" inserts original string\n \".*\" \"\\&_i\" attaches \"_i\" to original string\n \"\\(.*\\)_[io]$\" \"\\1\" strips off \"_i\" or \"_o\" from original string\n \".*\" \"foo\" inserts constant string \"foo\"\n \".*\" \"\" inserts empty string") (byte-code "\303\304\305\306\307\310\311\312&\210\303\313\305\314\311\304%\210\315\316\317\320\321DD\322\323\324\311\313&\210\303\325\305\326\311\304%\210\315\300\317\320\327DD\330\323\331\332\333\334\335\311\325& \210\315\336\317\320\337DD\340\323\305\203\\\341@@DB\262A\262\202H\342\237B\266\202\311\325&\210\315\343\317\320\344DD\345\334\346\323\324\311\325& \210\315\347\317\320\350DD\351\323\352\334\353\311\325& \210\315\354\317\320\355DD\356\323\357\311\325&\210\315\360\317\320\361DD\362\323\363\311\325&\210\303\364\305\365\311\304%\210\315\302\317\320\366DD\367\323\370\371\372\373\374\375\376\377\201@\372\201A\201B\201C\201D !\257\201E\201F\370\372\201G\374\201H\371\372\201I\374\201J\305\203\341@@DB\262A\262\202\356\201K\201L\237\"\266\202\201MBBBBBB\257\201NBBBBBBBBBBBD\332\201O\311\364& \210\315\364\317\320\201PDD\201Q\323\n\305\203S\341@@DB\262A\262\202?\201K\201R\237\"\266\202\311\364&\210\315\201S\317\320\201TDD\201U\323\201V\311\364&\207" [vhdl-compiler-alist default-directory vhdl-project-alist custom-declare-group vhdl nil "Customizations for VHDL Mode." :prefix "vhdl-" :group languages vhdl-mode "Customizations for modes." custom-declare-variable vhdl-indent-tabs-mode funcall function #[0 "\300\207" [nil] 1 #1=""] "Non-nil means indentation can insert tabs.\nOverrides local variable `indent-tabs-mode'." :type boolean vhdl-compile "Customizations for compilation." #[0 "\300\207" [(("ADVance MS" "vacom" "-work \\1" "make" "-f \\1" nil "valib \\1; vamap \\2 \\1" "./" "work/" "Makefile" "adms" ("^\\s-+\\([0-9]+\\):\\s-+" nil 1 nil nil) ("^Compiling file \\(.+\\)" 1) ("ENTI/\\1.vif" "ARCH/\\1-\\2.vif" "CONF/\\1.vif" "PACK/\\1.vif" "BODY/\\1.vif" upcase)) ("Aldec" "vcom" "-work \\1" "make" "-f \\1" nil "vlib \\1; vmap \\2 \\1" "./" "work/" "Makefile" "aldec" ("^.* ERROR [^:]+: \".*\" \"\\([^ \n]+\\)\" \\([0-9]+\\) \\([0-9]+\\)" 1 2 3 nil) (#1# 0) nil) ("Cadence Leapfrog" "cv" "-work \\1 -file" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "leapfrog" ("^duluth: \\*E,[0-9]+ (\\([^ \n]+\\),\\([0-9]+\\)):" 1 2 nil nil) (#1# 0) ("\\1/entity" "\\2/\\1" "\\1/configuration" "\\1/package" "\\1/body" downcase)) ("Cadence NC" "ncvhdl" "-work \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "ncvhdl" ("^ncvhdl_p: \\*E,\\w+ (\\([^ \n]+\\),\\([0-9]+\\)|\\([0-9]+\\)):" 1 2 3 nil) (#1# 0) ("\\1/entity/pc.db" "\\2/\\1/pc.db" "\\1/configuration/pc.db" "\\1/package/pc.db" "\\1/body/pc.db" downcase)) ("GHDL" "ghdl" "-i --workdir=\\1 --ieee=synopsys -fexplicit " "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "ghdl" ("^ghdl_p: \\*E,\\w+ (\\([^ \n]+\\),\\([0-9]+\\)|\\([0-9]+\\)):" 1 2 3 nil) (#1# 0) ("\\1/entity" "\\2/\\1" "\\1/configuration" "\\1/package" "\\1/body" downcase)) ("IBM Compiler" "g2tvc" "-src" "precomp" "\\1" nil "mkdir \\1" "./" "work/" "Makefile" "ibm" ("^[0-9]+ COACHDL.*: File: \\([^ \n]+\\), *line.column: \\([0-9]+\\).\\([0-9]+\\)" 1 2 3 nil) (" " 0) nil) ("Ikos" "analyze" "-l \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "ikos" ("^E L\\([0-9]+\\)/C\\([0-9]+\\):" nil 1 2 nil) ("^analyze +\\(.+ +\\)*\\(.+\\)$" 2) nil) ("ModelSim" "vcom" "-93 -work \\1" "make" "-f \\1" nil "vlib \\1; vmap \\2 \\1" "./" "work/" "Makefile" "modelsim" ("^\\(?:\\(?1:ERROR\\|\\*\\* Error\\)\\|\\(?2:WARNING\\|\\*\\* Warning\\)\\|\\(?3:NOTE\\|\\*\\* Note\\)\\)[^:]*:\\( *\\[[0-9]+]\\| ([^)]+)\\)? \\(?4:[^ \n]+\\)(\\(?5:[0-9]+\\)):" 4 5 nil (2 . 3)) (#1# 0) ("\\1/_primary.dat" "\\2/\\1.dat" "\\1/_primary.dat" "\\1/_primary.dat" "\\1/body.dat" downcase)) ("LEDA ProVHDL" "provhdl" "-w \\1 -f" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "provhdl" ("^\\([^ \n:]+\\):\\([0-9]+\\): " 1 2 nil nil) (#1# 0) ("ENTI/\\1.vif" "ARCH/\\1-\\2.vif" "CONF/\\1.vif" "PACK/\\1.vif" "BODY/BODY-\\1.vif" upcase)) ("Quartus" "make" "-work \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "quartus" ("^\\(Error\\|Warning\\): .* \\([^ \n]+\\)(\\([0-9]+\\))" 2 3 nil nil) (#1# 0) nil) ("QuickHDL" "qvhcom" "-work \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "quickhdl" ("^\\(ERROR\\|WARNING\\)[^:]*: \\([^ \n]+\\)(\\([0-9]+\\)):" 2 3 nil nil) (#1# 0) ("\\1/_primary.dat" "\\2/\\1.dat" "\\1/_primary.dat" "\\1/_primary.dat" "\\1/body.dat" downcase)) ("Savant" "scram" "-publish-cc -design-library-name \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work._savant_lib/" "Makefile" "savant" ("^\\([^ \n:]+\\):\\([0-9]+\\): " 1 2 nil nil) (#1# 0) ("\\1_entity.vhdl" "\\2_secondary_units._savant_lib/\\2_\\1.vhdl" "\\1_config.vhdl" "\\1_package.vhdl" "\\1_secondary_units._savant_lib/\\1_package_body.vhdl" downcase)) ("Simili" "vhdlp" "-work \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "simili" ("^\\(Error\\|Warning\\): \\w+: \\([^ \n]+\\): (line \\([0-9]+\\)): " 2 3 nil nil) (#1# 0) ("\\1/prim.var" "\\2/_\\1.var" "\\1/prim.var" "\\1/prim.var" "\\1/_body.var" downcase)) ("Speedwave" "analyze" "-libfile vsslib.ini -src" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "speedwave" ("^ *ERROR\\[[0-9]+]::File \\([^ \n]+\\) Line \\([0-9]+\\):" 1 2 nil nil) (#1# 0) nil) ("Synopsys" "vhdlan" "-nc -work \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "synopsys" ("^\\*\\*Error: vhdlan,[0-9]+ \\([^ \n]+\\)(\\([0-9]+\\)):" 1 2 nil nil) (#1# 0) ("\\1.sim" "\\2__\\1.sim" "\\1.sim" "\\1.sim" "\\1__.sim" upcase)) ("Synopsys Design Compiler" "vhdlan" "-nc -spc -work \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "synopsys_dc" ("^\\*\\*Error: vhdlan,[0-9]+ \\([^ \n]+\\)(\\([0-9]+\\)):" 1 2 nil nil) (#1# 0) ("\\1.syn" "\\2__\\1.syn" "\\1.syn" "\\1.syn" "\\1__.syn" upcase)) ("Synplify" "n/a" "n/a" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "synplify" ("^@[EWN]:\"\\([^ \n]+\\)\":\\([0-9]+\\):\\([0-9]+\\):" 1 2 3 nil) (#1# 0) nil) ("Vantage" "analyze" "-libfile vsslib.ini -src" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "vantage" ("^\\*\\*Error: LINE \\([0-9]+\\) \\*\\*\\*" nil 1 nil nil) ("^ *Compiling \"\\(.+\\)\" " 1) nil) ("VeriBest" "vc" "vhdl" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "veribest" ("^ +\\([0-9]+\\): +[^ ]" nil 1 nil nil) (#1# 0) nil) ("Viewlogic" "analyze" "-libfile vsslib.ini -src" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "viewlogic" ("^\\*\\*Error: LINE \\([0-9]+\\) \\*\\*\\*" nil 1 nil nil) ("^ *Compiling \"\\(.+\\)\" " 1) nil) ("Xilinx XST" "xflow" #1# "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "xilinx" ("^ERROR:HDLParsers:[0-9]+ - \"\\([^ \n]+\\)\" Line \\([0-9]+\\)\\." 1 2 nil nil) (#1# 0) nil) ("Xilinx Vivado" "xvhdl" #1# "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "vivado" ("^\\(?:\\(?1:ERROR\\)\\|\\(?2:WARNING\\)\\|\\(?3:INFO\\)\\): \\(.+\\) \\[\\(?4:[^ \n]+\\):\\(?5:[0-9]+\\)\\]" 4 5 nil (2 . 3)) (#1# 0) ("\\1/entity" "\\2/\\1" "\\1/configuration" "\\1/package" "\\1/body" downcase)))] 1 #1#] "List of available VHDL compilers and their properties.\nEach list entry specifies the following items for a compiler:\nCompiler:\n Compiler name : name used in option `vhdl-compiler' to choose compiler\n Compile command : command used for source file compilation\n Compile options : compile options (\"\\1\" inserts library name)\n Make command : command used for compilation using a Makefile\n Make options : make options (\"\\1\" inserts Makefile name)\n Generate Makefile: use built-in function or command to generate a Makefile\n (\"\\1\" inserts Makefile name, \"\\2\" inserts library name)\n Library command : command to create library directory (\"\\1\" inserts\n library directory, \"\\2\" inserts library name)\n Compile directory: where compilation is run and the Makefile is placed\n Library directory: directory of default library\n Makefile name : name of Makefile (default is \"Makefile\")\n ID string : compiler identification string (see `vhdl-project-alist')\nError message:\n Regexp : regular expression to match error messages (*)\n File subexp index: index of subexpression that matches the file name\n Line subexp index: index of subexpression that matches the line number\n Column subexp idx: index of subexpression that matches the column number\n Type subexp : message type, can be nil for a real error, 1 for warning\n or 0 for info. Type can also be detected using the form\n (WARNING . INFO). In that case this will be equivalent to\n 1 if the WARNING’th subexpression matched or else\n equivalent to 0 if the INFO’th subexpression matched, or\n else equivalent to nil if neither of them matched. See\n also `compilation-error-regexp-alist'.\nFile message:\n Regexp : regular expression to match a file name message\n File subexp index: index of subexpression that matches the file name\nUnit-to-file name mapping: mapping of library unit names to names of files\n generated by the compiler (used for Makefile generation)\n To string : string a name is mapped to (\"\\1\" inserts the unit name,\n \"\\2\" inserts the entity name for architectures,\n \"\\3\" inserts the library name)\n Case adjustment : adjust case of inserted unit names\n\n(*) The regular expression must match the error message starting from the\n beginning of the line (but not necessarily to the end of the line).\n\nCompile options allows insertion of the library name (see `vhdl-project-alist')\nin order to set the compilers library option (e.g. \"vcom -work my_lib\").\n\nFor Makefile generation, the built-in function can be used (requires\nspecification of the unit-to-file name mapping). Alternatively, an\nexternal command can be specified. Work directory allows specification of\nan alternative \"work\" library path (e.g. \"WORK/\" instead of \"work/\",\nused for Makefile generation). To use another library name than \"work\",\ncustomize `vhdl-project-alist'. The library command is inserted in Makefiles\nto automatically create the library directory if not existent.\n\nCompile options, compile directory, library directory, and Makefile name are\noverwritten by the project settings if a project is defined (see\n`vhdl-project-alist'). Directory paths are relative to the source file\ndirectory.\n\nSome compilers do not include the file name in the error message, but print\nout a file name message in advance. In this case, set \"File Subexp Index\"\nunder \"Error Message\" to 0 and fill out the \"File Message\" entries.\nIf no file name at all is printed out, set both \"File Message\" entries to 0\n(a default file name message will be printed out instead, does not work in\nXEmacs).\n\nA compiler is selected for syntax analysis (`\\[vhdl-compile]') by\nassigning its name to option `vhdl-compiler'.\n\nPlease send any missing or erroneous compiler properties to the maintainer for\nupdating.\n\nNOTE: Activate new error and file message regexps and reflect the new setting\n in the choice list of option `vhdl-compiler' by restarting Emacs." (repeat (list :tag "Compiler" :indent 2 (string :tag "Compiler name ") (string :tag "Compile command ") (string :tag "Compile options " "-work \\1") (string :tag "Make command " "make") (string :tag "Make options " "-f \\1") (choice :tag "Generate Makefile " (const :tag "Built-in function" nil) (string :tag "Command" "vmake \\2 > \\1")) (string :tag "Library command " "mkdir \\1") (directory :tag "Compile directory " :validate vhdl-widget-directory-validate "./") (directory :tag "Library directory " :validate vhdl-widget-directory-validate "work/") (file :tag "Makefile name " "Makefile") (string :tag "ID string ") (list :tag "Error message" :indent 4 (regexp :tag "Regexp ") (choice :tag "File subexp " (integer :tag "Index") (const :tag "No file name" nil)) (integer :tag "Line subexp index") (choice :tag "Column subexp " (integer :tag "Index") (const :tag "No column number" nil)) (choice :tag "Type " (const :tag "Info" 0) (const :tag "Warning" 1) (const :tag "Error" nil) (cons :tag "Type detection" (natnum :tag "Warning subexp index") (natnum :tag "Info subexp index ")))) (list :tag "File message" :indent 4 (regexp :tag "Regexp ") (integer :tag "File subexp index")) (choice :tag "Unit-to-file name mapping" :format "%t: %[Value Menu%] %v\n" (const :tag "Not defined" nil) (list :tag "To string" :indent 4 (string :tag "Entity " "\\1.vhd") (string :tag "Architecture " "\\2_\\1.vhd") (string :tag "Configuration " "\\1.vhd") (string :tag "Package " "\\1.vhd") (string :tag "Package Body " "\\1_body.vhd") (choice :tag "Case adjustment " (const :tag "None" identity) (const :tag "Upcase" upcase) (const :tag "Downcase" downcase)))))) :set #[514 "\300\301#\207" [vhdl-custom-set vhdl-update-mode-menu] 6 "\n\n(fn VARIABLE VALUE)"] :version "24.4" vhdl-compiler #[0 "\300\207" ["GHDL"] 1 #1#] "Specifies the VHDL compiler to be used for syntax analysis.\nSelect a compiler name from the ones defined in option `vhdl-compiler-alist'." const choice vhdl-compile-use-local-error-regexp #[0 "\300\207" [nil] 1 #1#] "Non-nil means use buffer-local `compilation-error-regexp-alist'.\nIn this case, only error message regexps for VHDL compilers are active if\ncompilation is started from a VHDL buffer. Otherwise, the error message\nregexps are appended to the predefined global regexps, and all regexps are\nactive all the time. Note that by doing that, the predefined global regexps\nmight result in erroneous parsing of error messages for some VHDL compilers.\n\nNOTE: Activate the new setting by restarting Emacs." "25.1" vhdl-makefile-default-targets #[0 "\300\207" [("all" "clean" "library")] 1 #1#] "List of default target names in Makefiles.\nAutomatically generated Makefiles include three default targets to compile\nthe entire design, clean the entire design and to create the design library.\nThis option allows you to change the names of these targets to avoid conflicts\nwith other user Makefiles." (list (string :tag "Compile entire design") (string :tag "Clean entire design ") (string :tag "Create design library")) "24.3" vhdl-makefile-generation-hook #[0 "\300\207" [nil] 1 #1#] "Functions to run at the end of Makefile generation.\nAllows you to insert user specific parts into a Makefile.\n\nExample:\n (lambda nil\n (re-search-backward \"^# Rule for compiling entire design\")\n (insert \"# My target\\n\\n.MY_TARGET :\\n\\n\\n\"))" hook vhdl-default-library #[0 "\300\207" ["work"] 1 #1#] "Name of default library.\nIs overwritten by project settings if a project is active." string vhdl-project "Customizations for projects." #[0 "\300\207" [(("Example 1" "Source files in two directories, custom library name, VHDL'87" "~/example1/" ("src/system/" "src/components/") #1# (("ModelSim" "-87 \\2" "-f \\1 top_level" nil) ("Synopsys" "-vhdl87 \\2" "-f \\1 top_level" ((".*/datapath/.*" . "-optimize \\3") (".*_tb\\.vhd")))) "lib/" "example3_lib" "lib/example3/" "Makefile_\\2" #1#) ("Example 2" "Individual source files, multiple compilers in different directories" "$EXAMPLE2/" ("vhdl/system.vhd" "vhdl/component_*.vhd") #1# nil "\\1/" "work" "\\1/work/" "Makefile" #1#) ("Example 3" "Source files in a directory tree, multiple compilers in same directory" "/home/me/example3/" ("-r ./*/vhdl/") "/CVS/" nil "./" "work" "work-\\1/" "Makefile-\\1" "-------------------------------------------------------------------------------\n-- This is a multi-line project description\n-- that can be used as a project dependent part of the file header.\n"))] 1 #1#] "List of projects and their properties.\n Name : name used in option `vhdl-project' to choose project\n Title : title of project (single-line string)\n Default directory: default project directory (absolute path)\n Sources : a) source files : path + \"/\" + file name\n b) directory : path + \"/\"\n c) directory tree: \"-r \" + path + \"/\"\n Exclude regexp : matches file/directory names to be excluded as sources\n Compile options : project-specific options for each compiler\n Compiler name : name of compiler for which these options are valid\n Compile options: project-specific compiler options\n (\"\\1\" inserts library name, \"\\2\" default options)\n Make options: project-specific make options\n (\"\\1\" inserts Makefile name, \"\\2\" default options)\n Exceptions : file-specific exceptions\n File name regexp: matches file names for which exceptions are valid\n - Options : file-specific compiler options string\n (\"\\1\" inserts library name, \"\\2\" default options,\n \"\\3\" project-specific options)\n - Do not compile: do not compile this file (in Makefile)\n Compile directory: where compilation is run and the Makefile is placed\n (\"\\1\" inserts compiler ID string)\n Library name : name of library (default is \"work\")\n Library directory: path to library (\"\\1\" inserts compiler ID string)\n Makefile name : name of Makefile\n (\"\\1\" inserts compiler ID string, \"\\2\" library name)\n Description : description of project (multi-line string)\n\nProject title and description are used to insert into the file header (see\noption `vhdl-file-header').\n\nThe default directory must have an absolute path (use `M-TAB' for completion).\nAll other paths can be absolute or relative to the default directory. All\npaths must end with `/'.\n\nThe design units found in the sources (files and directories) are shown in the\nhierarchy browser. Path and file name can contain wildcards `*' and `?' as\nwell as \"./\" and \"../\" (\"sh\" syntax). Paths can also be absolute.\nEnvironment variables (e.g. \"$EXAMPLE2\") are resolved. If no sources are\nspecified, the default directory is taken as source directory. Otherwise,\nthe default directory is only taken as source directory if there is a sources\nentry with the empty string or \"./\". Exclude regexp allows you to filter\nout specific file and directory names from the list of sources (e.g. CVS\ndirectories).\n\nFiles are compiled in the compile directory. Makefiles are also placed into\nthe compile directory. Library directory specifies which directory the\ncompiler compiles into (used to generate the Makefile).\n\nSince different compile/library directories and Makefiles may exist for\ndifferent compilers within one project, these paths and names allow the\ninsertion of a compiler-dependent ID string (defined in `vhdl-compiler-alist').\nCompile options, compile directory, library directory, and Makefile name\noverwrite the settings of the current compiler.\n\nFile-specific compiler options (highest priority) overwrite project-specific\noptions which overwrite default options (lowest priority). Lower priority\noptions can be inserted in higher priority options. This allows you to reuse\ndefault options (e.g. \"-file\") in project- or file-specific options (e.g.\n\"-93 -file\").\n\nNOTE: Reflect the new setting in the choice list of option `vhdl-project'\n by restarting Emacs." repeat list :tag "Project" :indent 2 (string :tag "Name ") (string :tag "Title ") directory "Default directory" :validate vhdl-widget-directory-validate abbreviate-file-name (repeat :tag "Sources " :indent 4 (directory :format " %v" "./")) (regexp :tag "Exclude regexp ") "Compile options " 4 "Compiler" 6 append (choice :tag "Compiler name") ((string :tag "Compile options" "\\2") (string :tag "Make options " "\\2") (repeat :tag "Exceptions " :indent 8 (cons :format "%v" (regexp :tag "File name regexp ") (choice :format "%[Value Menu%] %v" (string :tag "Options" "\\3") (const :tag "Do not compile" nil))))) ((directory :tag "Compile directory" :validate vhdl-widget-directory-validate "./") (string :tag "Library name " "work") (directory :tag "Library directory" :validate vhdl-widget-directory-validate "work/") (file :tag "Makefile name " "Makefile") (string :tag "Description: (type `C-j' for newline)" :format "%t\n%v\n")) #[514 "\300\301\302$\207" [vhdl-custom-set vhdl-update-mode-menu vhdl-speedbar-refresh] 7 "\n\n(fn VARIABLE VALUE)"] #[0 "\300\207" [nil] 1 #1#] "Specifies the default for the current project.\nSelect a project name from the ones defined in option `vhdl-project-alist'.\nIs used to determine the project title and description to be inserted in file\nheaders and the source files/directories to be scanned in the hierarchy\nbrowser. The current project can also be changed temporarily in the menu." (choice (const :tag "None" nil) (const :tag "--")) vhdl-project-file-name #[0 "\300\207" [("\\1.prj")] 1 #1#] "List of file names/paths for importing/exporting project setups.\n\"\\1\" is replaced by the project name (SPC is replaced by `_'), \"\\2\" is\nreplaced by the user name (allows you to have user-specific project setups).\nThe first entry is used as file name to import/export individual project\nsetups. All entries are used to automatically import project setups at\nstartup (see option `vhdl-project-autoload'). Projects loaded from the\nfirst entry are automatically made current. Hint: specify local project\nsetups in first entry, global setups in following entries; loading a local\nproject setup will make it current, while loading the global setups\nis done without changing the current project.\nNames can also have an absolute path (i.e. project setups can be stored\nin global directories)." (repeat (string :tag "File name" "\\1.prj"))] 31) (byte-code "\301\302\303\304#\210\305\211\203(\211@\302N\203!\303N\204!\306\303\302N#\210A\266\202\202\210\307\302\303\310#\210\311\303\312\313\314DD\315\316\317\320\321&\210\311\322\312\313\323DD\324\316\325\320\321&\210\326\327\304\330\320\331\320\332\320\333\320\334& \210\311\335\312\313\336DD\337\316\340\341\342\320\327& \210\311\343\312\313\344DD\345\316\346\320\327&\210\311\347\312\313\350DD\351\316\325\341\352\320\327& \210\311\353\312\313\354DD\355\316\325\341\356\320\327& \210\311\357\312\313\360DD\361\316\325\341\362\320\327& \210\311\363\312\313\364DD\365\316\325\341\366\320\327& \210\311\367\312\313\370DD\371\316\325\341\372\320\327& \210\311\373\312\313\374DD\375\316\376\320\327&\210\311\377\312\313\201@DD\201A\316\325\201B\201C\320\327& \210\326\201D\304\201E\320\331%\210\311\201F\312\313\201GDD\201HP\316\201I\320\201D\320\334& \210\311\201J\312\313\201KDD\201LP\316\201M\320\201D\320\334& \210\311\201N\312\313\201ODD\201PP\316\201Q\320\201D\320\334& \210\311\201R\312\313\201SDD\201TP\316\201U\320\201D\320\334& \207" [vhdl-name-doc-string defvaralias vhdl-project-auto-load vhdl-project-autoload nil (saved-value saved-variable-comment) put make-obsolete-variable "27.1" custom-declare-variable funcall function #[0 "\300\207" [(startup)] 1 #1=""] "Automatically load project setups from files.\nAll project setup files that match the file names specified in option\n`vhdl-project-file-name' are automatically loaded. The project of the\n(alphabetically) last loaded setup of the first `vhdl-project-file-name'\nentry is activated.\nA project setup file can be obtained by exporting a project (see menu).\n At startup: project setup file is loaded at Emacs startup." :type (set (const :tag "At startup" startup)) :group vhdl-project vhdl-project-sort #[0 "\300\207" [t] 1 #1#] "Non-nil means projects are displayed in alphabetical order." boolean custom-declare-group vhdl-style "Customizations for coding styles." vhdl vhdl-template vhdl-port vhdl-compose vhdl-standard #[0 "\300\207" [(93 nil)] 1 #1#] "VHDL standards used.\nBasic standard:\n VHDL'87 : IEEE Std 1076-1987\n VHDL'93/02 : IEEE Std 1076-1993/2002\n VHDL'08 : IEEE Std 1076-2008\nAdditional standards:\n VHDL-AMS : IEEE Std 1076.1 (analog-mixed-signal)\n Math packages: IEEE Std 1076.2 (`math_real', `math_complex')\n\nNOTE: Activate the new setting in a VHDL buffer by using the menu entry\n \"Activate Options\"." (list (choice :tag "Basic standard" (const :tag "VHDL'87" 87) (const :tag "VHDL'93/02" 93) (const :tag "VHDL'08" 8)) (set :tag "Additional standards" :indent 2 (const :tag "VHDL-AMS" ams) (const :tag "Math packages" math))) :set #[514 "\300\301\302\303\304\305\306\307& \207" [vhdl-custom-set vhdl-template-map-init vhdl-mode-abbrev-table-init vhdl-template-construct-alist-init vhdl-template-package-alist-init vhdl-update-mode-menu vhdl-words-init vhdl-font-lock-init] 12 "\n\n(fn VARIABLE VALUE)"] vhdl-basic-offset #[0 "\300\207" [2] 1 #1#] "Amount of basic offset used for indentation.\nThis value is used by + and - symbols in `vhdl-offsets-alist'." integer vhdl-upper-case-keywords #[0 "\300\207" [nil] 1 #1#] "Non-nil means convert keywords to upper case.\nThis is done when typed or expanded or by the fix case functions." #[514 "\300\301#\207" [vhdl-custom-set vhdl-abbrev-list-init] 6 "\n\n(fn VARIABLE VALUE)"] vhdl-upper-case-types #[0 "\300\207" [nil] 1 #1#] "Non-nil means convert standardized types to upper case.\nThis is done when expanded or by the fix case functions." #[514 "\300\301#\207" [vhdl-custom-set vhdl-abbrev-list-init] 6 "\n\n(fn VARIABLE VALUE)"] vhdl-upper-case-attributes #[0 "\300\207" [nil] 1 #1#] "Non-nil means convert standardized attributes to upper case.\nThis is done when expanded or by the fix case functions." #[514 "\300\301#\207" [vhdl-custom-set vhdl-abbrev-list-init] 6 "\n\n(fn VARIABLE VALUE)"] vhdl-upper-case-enum-values #[0 "\300\207" [nil] 1 #1#] "Non-nil means convert standardized enumeration values to upper case.\nThis is done when expanded or by the fix case functions." #[514 "\300\301#\207" [vhdl-custom-set vhdl-abbrev-list-init] 6 "\n\n(fn VARIABLE VALUE)"] vhdl-upper-case-constants #[0 "\300\207" [t] 1 #1#] "Non-nil means convert standardized constants to upper case.\nThis is done when expanded." #[514 "\300\301#\207" [vhdl-custom-set vhdl-abbrev-list-init] 6 "\n\n(fn VARIABLE VALUE)"] vhdl-use-direct-instantiation #[0 "\300\207" [standard] 1 #1#] "Non-nil means use VHDL'93 direct component instantiation.\n Never : never\n Standard: only in VHDL standards that allow it (VHDL'93 and higher)\n Always : always" (choice (const :tag "Never" never) (const :tag "Standard" standard) (const :tag "Always" always)) vhdl-array-index-record-field-in-sensitivity-list #[0 "\300\207" [t] 1 #1#] "Non-nil means include array indices / record fields in sensitivity list.\nIf a signal read in a process is a record field or pointed to by an array\nindex, the record field or array index is included with the record name in\nthe sensitivity list (e.g. \"in1(0)\", \"in2.f0\").\nOtherwise, only the record name is included (e.g. \"in1\", \"in2\")." :version "24.3" vhdl-naming "Customizations for naming conventions." vhdl-entity-file-name #[0 "\300\207" [(".*" . "\\&")] 1 #1#] "Specifies how the entity file name is obtained.\nThe entity file name can be obtained by modifying the entity name (e.g.\nattaching or stripping off a substring). The file extension is automatically\ntaken from the file name of the current buffer." (cons (regexp :tag "From regexp") (string :tag "To string ")) vhdl-architecture-file-name #[0 "\300\207" [("\\(.*\\) \\(.*\\)" . "\\1_\\2")] 1 #1#] "Specifies how the architecture file name is obtained.\nThe architecture file name can be obtained by modifying the entity\nand/or architecture name (e.g. attaching or stripping off a substring). The\nfile extension is automatically taken from the file name of the current\nbuffer. The string that is matched against the regexp is the concatenation\nof the entity and the architecture name separated by a space. This gives\naccess to both names (see default setting as example)." (cons (regexp :tag "From regexp") (string :tag "To string ")) vhdl-configuration-file-name #[0 "\300\207" [(".*" . "\\&")] 1 #1#] "Specifies how the configuration file name is obtained.\nThe configuration file name can be obtained by modifying the configuration\nname (e.g. attaching or stripping off a substring). The file extension is\nautomatically taken from the file name of the current buffer." (cons (regexp :tag "From regexp") (string :tag "To string ")) vhdl-package-file-name #[0 "\300\207" [(".*" . "\\&")] 1 #1#] "Specifies how the package file name is obtained.\nThe package file name can be obtained by modifying the package name (e.g.\nattaching or stripping off a substring). The file extension is automatically\ntaken from the file name of the current buffer. Package files can be created\nin a different directory by prepending a relative or absolute path to the\nfile name." (cons (regexp :tag "From regexp") (string :tag "To string "))] 12) (byte-code "\300\301\302\303\304DD\305\306\307\310\311\310\312& \210\313\314\315\316\310\317%\210\300\320\302\303\321DD\322\306\323\324\325\310\314& \210\300\326\302\303\327DD\330\306\331\310\314&\210\300\332\302\303\333DD\334\306\335\310\314\310\336\310\312& \210\300\337\302\303\340DD\341\306\342\310\314\310\336\310\312& \210\300\343\302\303\344DD\345\306\342\310\314\310\336\310\312& \210\300\346\302\303\347DD\350\306\342\310\314&\210\300\351\302\303\352DD\353\354\355\306\342\310\314& \210\300\356\302\303\357DD\360\306\361\310\314&\210\300\362\302\303\363DD\364\306\361\310\314&\210\313\365\315\366\310\314\310\312&\210\300\367\302\303\370DD\371\306\361\310\365&\210\300\372\302\303\373DD\374\306\361\310\365&\210\300\375\302\303\376DD\377\306\361\310\365&\210\300\201@\302\303\201ADD\201B\306\361\310\365&\210\300\201C\302\303\201DDD\201E\306\361\310\365&\210\300\201F\302\303\201GDD\201H\306\361\310\365&\210\300\201I\302\303\201JDD\201K\306\361\310\365&\210\300\201L\302\303\201MDD\201N\306\342\310\365&\210\313\201O\315\201P\310\314%\210\300\201Q\302\303\201RDD\201S\306\201T\310\201O&\207" [custom-declare-variable vhdl-file-name-case funcall function #[0 "\300\207" [identity] 1 #1=""] "Specifies how to change case for obtaining file names.\nWhen deriving a file name from a VHDL unit name, case can be changed as\nfollows:\n As Is: case is not changed (taken as is)\n Lower Case: whole name is changed to lower case\n Upper Case: whole name is changed to upper case\n Capitalize: first letter of each word in name is capitalized" :type (choice (const :tag "As Is" identity) (const :tag "Lower Case" downcase) (const :tag "Upper Case" upcase) (const :tag "Capitalize" capitalize)) :group vhdl-naming vhdl-compose custom-declare-group vhdl-template nil "Customizations for electrification." vhdl vhdl-electric-keywords #[0 "\300\207" [(vhdl user)] 1 #1#] "Type of keywords for which electrification is enabled.\n VHDL keywords: invoke built-in templates\n User keywords: invoke user models (see option `vhdl-model-alist')" (set (const :tag "VHDL keywords" vhdl) (const :tag "User model keywords" user)) :set #[514 "\300\301#\207" [vhdl-custom-set vhdl-mode-abbrev-table-init] 6 "\n\n(fn VARIABLE VALUE)"] vhdl-optional-labels #[0 "\300\207" [process] 1 #1#] "Constructs for which labels are to be queried.\nTemplate generators prompt for optional labels for:\n None : no constructs\n Processes only: processes only (also procedurals in VHDL-AMS)\n All constructs: all constructs with optional labels and keyword END" (choice (const :tag "None" none) (const :tag "Processes only" process) (const :tag "All constructs" all)) vhdl-insert-empty-lines #[0 "\300\207" [unit] 1 #1#] "Specifies whether to insert empty lines in some templates.\nThis improves readability of code. Empty lines are inserted in:\n None : no constructs\n Design units only: entities, architectures, configurations, packages only\n All constructs : also all constructs with BEGIN...END parts\n\nReplaces option `vhdl-additional-empty-lines'." (choice (const :tag "None" none) (const :tag "Design units only" unit) (const :tag "All constructs" all)) vhdl-port vhdl-argument-list-indent #[0 "\300\207" [nil] 1 #1#] "Non-nil means indent argument lists relative to opening parenthesis.\nThat is, argument, association, and port lists start on the same line as the\nopening parenthesis and subsequent lines are indented accordingly.\nOtherwise, lists start on a new line and are indented as normal code." boolean vhdl-association-list-with-formals #[0 "\300\207" [t] 1 #1#] "Non-nil means write association lists with formal parameters.\nTemplates prompt for formal and actual parameters (ports/generics).\nWhen pasting component instantiations, formals are included.\nIf nil, only a list of actual parameters is entered." vhdl-conditions-in-parenthesis #[0 "\300\207" [nil] 1 #1#] "Non-nil means place parenthesis around condition expressions." vhdl-sensitivity-list-all #[0 "\300\207" [t] 1 #1#] "Non-nil means use `all' keyword in sensitivity list." :version "25.1" vhdl-zero-string #[0 "\300\207" ["'0'"] 1 #1#] "String to use for a logic zero." string vhdl-one-string #[0 "\300\207" ["'1'"] 1 #1#] "String to use for a logic one." vhdl-header "Customizations for file header." vhdl-file-header #[0 "\300\207" ["-------------------------------------------------------------------------------\n-- Title : \n-- Project : <project>\n-------------------------------------------------------------------------------\n-- File : <filename>\n-- Author : <author>\n-- Company : <company>\n-- Created : <date>\n-- Last update: <date>\n-- Platform : <platform>\n-- Standard : <standard>\n<projectdesc>-------------------------------------------------------------------------------\n-- Description: <cursor>\n<copyright>-------------------------------------------------------------------------------\n-- Revisions :\n-- Date Version Author Description\n-- <date> 1.0 <login> Created\n-------------------------------------------------------------------------------\n\n"] 1 #1#] "String or file to insert as file header.\nIf the string specifies an existing file name, the contents of the file is\ninserted, otherwise the string itself is inserted as file header.\nType `C-j' for newlines.\nIf the header contains RCS keywords, they may be written as <RCS>Keyword<RCS>\nif the header needs to be version controlled.\n\nThe following keywords for template generation are supported:\n <filename> : replaced by the name of the buffer\n <author> : replaced by the user name and email address\n (`user-full-name', `user-mail-address')\n <authorfull> : replaced by the user full name (`user-full-name')\n <login> : replaced by user login name (`user-login-name')\n <company> : replaced by contents of option `vhdl-company-name'\n <date> : replaced by the current date\n <year> : replaced by the current year\n <project> : replaced by title of current project (`vhdl-project')\n <projectdesc> : replaced by description of current project (`vhdl-project')\n <copyright> : replaced by copyright string (`vhdl-copyright-string')\n <platform> : replaced by contents of option `vhdl-platform-spec'\n <standard> : replaced by the VHDL language standard(s) used\n <... string> : replaced by a queried string (\"...\" is the prompt word)\n <title string>: replaced by file title in automatically generated files\n <cursor> : final cursor position\n\nThe (multi-line) project description <projectdesc> can be used as a project\ndependent part of the file header and can also contain the above keywords." vhdl-file-footer #[0 "\300\207" [#1#] 1 #1#] "String or file to insert as file footer.\nIf the string specifies an existing file name, the contents of the file is\ninserted, otherwise the string itself is inserted as file footer (i.e. at\nthe end of the file).\nType `C-j' for newlines.\nThe same keywords as in option `vhdl-file-header' can be used." vhdl-company-name #[0 "\300\207" [#1#] 1 #1#] "Name of company to insert in file header.\nSee option `vhdl-file-header'." vhdl-copyright-string #[0 "\300\207" ["-------------------------------------------------------------------------------\n-- Copyright (c) <year> <company>\n"] 1 #1#] "Copyright string to insert in file header.\nCan be multi-line string (type `C-j' for newline) and contain other file\nheader keywords (see option `vhdl-file-header')." vhdl-platform-spec #[0 "\300\207" [#1#] 1 #1#] "Specification of VHDL platform to insert in file header.\nThe platform specification should contain names and versions of the\nsimulation and synthesis tools used.\nSee option `vhdl-file-header'." vhdl-date-format #[0 "\300\207" ["%Y-%m-%d"] 1 #1#] "Specifies the date format to use in the header.\nThis string is passed as argument to the command `format-time-string'.\nFor more information on format strings, see the documentation for the\n`format-time-string' command (C-h f `format-time-string')." vhdl-modify-date-prefix-string #[0 "\300\207" ["-- Last update: "] 1 #1#] "Prefix string of modification date in VHDL file header.\nIf actualization of the modification date is called (menu,\n`\\[vhdl-template-modify]'), this string is searched and the rest\nof the line replaced by the current date." vhdl-modify-date-on-saving #[0 "\300\207" [t] 1 #1#] "Non-nil means update the modification date when the buffer is saved.\nCalls function `\\[vhdl-template-modify]').\n\nNOTE: Activate the new setting in a VHDL buffer by using the menu entry\n \"Activate Options\"." vhdl-sequential-process "Customizations for sequential processes." vhdl-reset-kind #[0 "\300\207" [async] 1 #1#] "Specifies which kind of reset to use in sequential processes." (choice (const :tag "None" none) (const :tag "Synchronous" sync) (const :tag "Asynchronous" async) (const :tag "Query" query))] 12) (byte-code "\301\302\303\304\305DD\306\307\310\311\312&\210\301\313\303\304\314DD\315\307\310\311\312&\210\301\316\303\304\317DD\320\307\321\311\312&\210\301\322\303\304\323DD\324\307\325\311\312&\210\301\326\303\304\327DD\330\307\325\311\312&\210\331\332\333\334\311\335%\210\301\336\303\304\337DD\340\307\341\342\343\311\332& \210\331\344\333\345\311\335%\210\301\346\303\304\347DD\350P\307\351\311\344&\210\301\352\303\304\353DD\354P\307\355\311\344&\210\301\356\303\304\357DD\360P\307\361\311\344&\210\301\362\303\304\363DD\364\307\310\311\344&\210\301\365\303\304\366DD\367\307\310\311\344&\210\301\370\303\304\371DD\372\307\373\311\344&\210\301\374\303\304\375DD\376\307\310\311\344&\210\301\377\303\304\201@�DD\201A�\307\310\311\344&\210\301\201B�\303\304\201C�DD\201D�\307\310\311\344&\210\331\201E�\333\201F�\311\335\311\344&\210\301\201G�\303\304\201H�DD\201I�\307\310\311\201E�&\210\301\201J�\303\304\201K�DD\201L�\307\310\311\201E�&\210\301\201M�\303\304\201N�DD\201O�\307\310\311\201E�&\210\301\201P�\303\304\201Q�DD\201R�\307\201S�\311\201E�&\210\301\201T�\303\304\201U�DD\201V�P\307\201W�\311\201E�\201X�\201Y�& \207" [vhdl-name-doc-string custom-declare-variable vhdl-reset-active-high funcall function #[0 "\300\207" [nil] 1 #1=""] "Non-nil means reset in sequential processes is active high.\nOtherwise, reset is active low." :type boolean :group vhdl-sequential-process vhdl-clock-rising-edge #[0 "\300\207" [t] 1 #1#] "Non-nil means rising edge of clock triggers sequential processes.\nOtherwise, falling edge triggers." vhdl-clock-edge-condition #[0 "\300\207" [standard] 1 #1#] "Syntax of the clock edge condition.\n Standard: \"clk\\='event and clk = \\='1\\='\"\n Function: \"rising_edge(clk)\"" (choice (const :tag "Standard" standard) (const :tag "Function" function)) vhdl-clock-name #[0 "\300\207" [#1#] 1 #1#] "Name of clock signal to use in templates." string vhdl-reset-name #[0 "\300\207" [#1#] 1 #1#] "Name of reset signal to use in templates." custom-declare-group vhdl-model nil "Customizations for user models." vhdl vhdl-model-alist #[0 "\300\207" [(("Example Model" "<label> : process (<clock>, <reset>)\nbegin -- process <label>\n if <reset> = '0' then -- asynchronous reset (active low)\n <cursor>\n elsif <clock>'event and <clock> = '1' then -- rising clock edge\n if <enable> = '1' then -- synchronous load\n\n end if;\n end if;\nend process <label>;" "e" #1#))] 1 #1#] "List of user models.\nVHDL models (templates) can be specified by the user in this list. They can be\ninvoked from the menu, through key bindings (`C-c C-m ...'), or by keyword\nelectrification (i.e. overriding existing or creating new keywords, see\noption `vhdl-electric-keywords').\n Name : name of model (string of words and spaces)\n String : string or name of file to be inserted as model (newline: `C-j')\n Key Binding: key binding to invoke model, added to prefix `C-c C-m'\n (must be in double-quotes, examples: \"i\", \"\\C-p\", \"\\M-s\")\n Keyword : keyword to invoke model\n\nThe models can contain prompts to be queried. A prompt is of the form \"<...>\".\nA prompt that appears several times is queried once and replaced throughout\nthe model. Special prompts are:\n <clock> : name specified in `vhdl-clock-name' (if not empty)\n <reset> : name specified in `vhdl-reset-name' (if not empty)\n <cursor>: final cursor position\nFile header prompts (see variable `vhdl-file-header') are automatically\nreplaced, so that user models can also be used to insert different types of\nheaders.\n\nIf the string specifies an existing file name, the contents of the file is\ninserted, otherwise the string itself is inserted.\nThe code within the models should be correctly indented.\nType `C-j' for newlines.\n\nNOTE: Activate the new setting in a VHDL buffer by using the menu entry\n \"Activate Options\"." (repeat (list :tag "Model" :indent 2 (string :tag "Name ") (string :tag "String : (type `C-j' for newline)" :format "%t\n%v") (sexp :tag "Key binding" x) (string :tag "Keyword " :format "%t: %v\n"))) :set #[514 "\300\301\302\303\304&\207" [vhdl-custom-set vhdl-model-map-init vhdl-model-defun vhdl-mode-abbrev-table-init vhdl-update-mode-menu] 9 "\n\n(fn VARIABLE VALUE)"] vhdl-compose "Customizations for structural composition." vhdl-compose-architecture-name #[0 "\300\207" [(".*" . "str")] 1 #1#] "Specifies how the component architecture name is obtained.\nThe component architecture name can be obtained by modifying the entity name\n(e.g. attaching or stripping off a substring).\nIf TO STRING is empty, the architecture name is queried." (cons (regexp :tag "From regexp") (string :tag "To string ")) vhdl-compose-configuration-name #[0 "\300\207" [("\\(.*\\) \\(.*\\)" . "\\1_\\2_cfg")] 1 #1#] "Specifies how the configuration name is obtained.\nThe configuration name can be obtained by modifying the entity and/or\narchitecture name (e.g. attaching or stripping off a substring). The string\nthat is matched against the regexp is the concatenation of the entity and the\narchitecture name separated by a space. This gives access to both names (see\ndefault setting as example)." (cons (regexp :tag "From regexp") (string :tag "To string ")) vhdl-components-package-name #[0 "\300\207" [((".*" . "\\&_components") . "components")] 1 #1#] "Specifies how the name for the components package is obtained.\nThe components package is a package containing all component declarations for\nthe current design. Its name can be obtained by modifying the project name\n(e.g. attaching or stripping off a substring). If no project is defined, the\nDIRECTORY entry is chosen." (cons (cons :tag "Project" :indent 2 (regexp :tag "From regexp") (string :tag "To string ")) (string :tag "Directory:\n String ")) vhdl-use-components-package #[0 "\300\207" [nil] 1 #1#] "Non-nil means use a separate components package for component declarations.\nOtherwise, component declarations are inserted and searched for in the\narchitecture declarative parts." vhdl-compose-include-header #[0 "\300\207" [t] 1 #1#] "Non-nil means include a header in automatically generated files." vhdl-compose-create-files #[0 "\300\207" [single] 1 #1#] "Specifies whether new files should be created for the new component.\nThe component's entity and architecture are inserted:\n None : in current buffer\n Single file : in new single file\n Separate files: in two separate files\nThe file names are obtained from variables `vhdl-entity-file-name' and\n`vhdl-architecture-file-name'." (choice (const :tag "None" none) (const :tag "Single file" single) (const :tag "Separate files" separate)) vhdl-compose-configuration-create-file #[0 "\300\207" [nil] 1 #1#] "Specifies whether a new file should be created for the configuration.\nIf non-nil, a new file is created for the configuration.\nThe file name is obtained from variable `vhdl-configuration-file-name'." vhdl-compose-configuration-hierarchical #[0 "\300\207" [t] 1 #1#] "Specifies whether hierarchical configurations should be created.\nIf non-nil, automatically created configurations are hierarchical and include\nthe whole hierarchy of subcomponents. Otherwise the configuration only\nincludes one level of subcomponents." vhdl-compose-configuration-use-subconfiguration #[0 "\300\207" [t] 1 #1#] "Specifies whether subconfigurations should be used inside configurations.\nIf non-nil, automatically created configurations use configurations in binding\nindications for subcomponents, if such configurations exist. Otherwise,\nentities are used in binding indications for subcomponents." vhdl-port "Customizations for port translation functions." vhdl-include-port-comments #[0 "\300\207" [nil] 1 #1#] "Non-nil means include port comments when a port is pasted." vhdl-include-direction-comments #[0 "\300\207" [nil] 1 #1#] "Non-nil means include port direction in instantiations as comments." vhdl-include-type-comments #[0 "\300\207" [nil] 1 #1#] "Non-nil means include generic/port type in instantiations as comments." vhdl-include-group-comments #[0 "\300\207" [never] 1 #1#] "Specifies whether to include group comments and spacings.\nThe comments and empty lines between groups of ports are pasted:\n Never : never\n Declarations: in entity/component/constant/signal declarations only\n Always : also in generic/port maps" (choice (const :tag "Never" never) (const :tag "Declarations" decl) (const :tag "Always" always)) vhdl-actual-generic-name #[0 "\300\207" [(".*" . "\\&")] 1 #1#] "Specifies how actual generic names are obtained from formal generic names.\nIn a component instantiation, an actual generic name can be\nobtained by modifying the formal generic name (e.g. attaching or stripping\noff a substring)." (cons (regexp :tag "From regexp") (string :tag "To string ")) :version "24.4"] 10) (byte-code "\301\302\303\304\305DD\306P\307\310\311\312&\210\301\313\303\304\314DD\315P\307\316\311\312&\210\317\320\321\322\311\312%\210\301\323\303\304\324DD\325P\307\326\311\320&\210\301\327\303\304\330DD\331P\307\332\311\320&\210\301\333\303\304\334DD\335P\307\336\311\320&\210\301\337\303\304\340DD\341P\307\342\311\320&\210\301\343\303\304\344DD\345\307\346\311\320&\210\301\347\303\304\350DD\351\307\352\311\320&\210\301\353\303\304\354DD\355\307\352\311\320&\210\301\356\303\304\357DD\360\307\346\311\320&\210\301\361\303\304\362DD\363\307\346\311\320&\210\301\364\303\304\365DD\366\307\346\311\320&\210\301\367\303\304\370DD\371\307\372\311\320&\210\301\373\303\304\374DD\375P\307\376\311\320&\210\301\377\303\304\201@�DD\201A�P\307\201B�\311\320&\210\317\201C�\321\201D�\311\201E�%\210\301\201F�\303\304\201G�DD\201H�\307\346\311\201C�&\210\301\201I�\303\304\201J�DD\201K�\307\346\311\201C�&\210\301\201L�\303\304\201M�DD\201N�\307\201O�\311\201C�&\210\301\201P�\303\304\201Q�DD\201R�\307\201O�\311\201C�&\210\317\201S�\321\201T�\311\201E�%\207" [vhdl-name-doc-string custom-declare-variable vhdl-actual-port-name funcall function #[0 "\300\207" [(".*" . "\\&")] 1 #1=""] "Specifies how actual port names are obtained from formal port names.\nIn a component instantiation, an actual port name can be obtained by\nmodifying the formal port name (e.g. attaching or stripping off a substring)." :type (cons (regexp :tag "From regexp") (string :tag "To string ")) :group vhdl-port vhdl-instance-name #[0 "\300\207" [(".*" . "\\&_%d")] 1 #1#] "Specifies how an instance name is obtained.\nThe instance name can be obtained by modifying the name of the component to be\ninstantiated (e.g. attaching or stripping off a substring). \"%d\" is replaced\nby a unique number (starting with 1).\nIf TO STRING is empty, the instance name is queried." (cons (regexp :tag "From regexp") (string :tag "To string ")) custom-declare-group vhdl-testbench nil "Customizations for testbench generation." vhdl-testbench-entity-name #[0 "\300\207" [(".*" . "\\&_tb")] 1 #1#] "Specifies how the testbench entity name is obtained.\nThe entity name of a testbench can be obtained by modifying the name of\nthe component to be tested (e.g. attaching or stripping off a substring)." (cons (regexp :tag "From regexp") (string :tag "To string ")) vhdl-testbench-architecture-name #[0 "\300\207" [(".*" . #1#)] 1 #1#] "Specifies how the testbench architecture name is obtained.\nThe testbench architecture name can be obtained by modifying the name of\nthe component to be tested (e.g. attaching or stripping off a substring).\nIf TO STRING is empty, the architecture name is queried." (cons (regexp :tag "From regexp") (string :tag "To string ")) vhdl-testbench-configuration-name #[0 "\207" [vhdl-compose-configuration-name] 1 #1#] "Specifies how the testbench configuration name is obtained.\nThe configuration name of a testbench can be obtained by modifying the entity\nand/or architecture name (e.g. attaching or stripping off a substring). The\nstring that is matched against the regexp is the concatenation of the entity\nand the architecture name separated by a space. This gives access to both\nnames (see default setting as example)." (cons (regexp :tag "From regexp") (string :tag "To string ")) vhdl-testbench-dut-name #[0 "\300\207" [(".*" . "DUT")] 1 #1#] "Specifies how a DUT instance name is obtained.\nThe design-under-test instance name (i.e. the component instantiated in the\ntestbench) can be obtained by modifying the component name (e.g. attaching\nor stripping off a substring)." (cons (regexp :tag "From regexp") (string :tag "To string ")) vhdl-testbench-include-header #[0 "\300\207" [t] 1 #1#] "Non-nil means include a header in automatically generated files." boolean vhdl-testbench-declarations #[0 "\300\207" [" -- clock\n signal Clk : std_logic := '1';\n"] 1 #1#] "String or file to be inserted in the testbench declarative part.\nIf the string specifies an existing file name, the contents of the file is\ninserted, otherwise the string itself is inserted in the testbench\narchitecture before the BEGIN keyword.\nType `C-j' for newlines." string vhdl-testbench-statements #[0 "\300\207" [" -- clock generation\n Clk <= not Clk after 10 ns;\n\n -- waveform generation\n WaveGen_Proc: process\n begin\n -- insert signal assignments here\n\n wait until Clk = '1';\n end process WaveGen_Proc;\n"] 1 #1#] "String or file to be inserted in the testbench statement part.\nIf the string specifies an existing file name, the contents of the file is\ninserted, otherwise the string itself is inserted in the testbench\narchitecture before the END keyword.\nType `C-j' for newlines." vhdl-testbench-initialize-signals #[0 "\300\207" [nil] 1 #1#] "Non-nil means initialize signals with `0' when declared in testbench." vhdl-testbench-include-library #[0 "\300\207" [t] 1 #1#] "Non-nil means a library/use clause for std_logic_1164 is included." vhdl-testbench-include-configuration #[0 "\300\207" [t] 1 #1#] "Non-nil means a testbench configuration is attached at the end." vhdl-testbench-create-files #[0 "\300\207" [single] 1 #1#] "Specifies whether new files should be created for the testbench.\ntestbench entity and architecture are inserted:\n None : in current buffer\n Single file : in new single file\n Separate files: in two separate files\nThe file names are obtained from variables `vhdl-testbench-entity-file-name'\nand `vhdl-testbench-architecture-file-name'." (choice (const :tag "None" none) (const :tag "Single file" single) (const :tag "Separate files" separate)) vhdl-testbench-entity-file-name #[0 "\207" [vhdl-entity-file-name] 1 #1#] "Specifies how the testbench entity file name is obtained.\nThe entity file name can be obtained by modifying the testbench entity name\n(e.g. attaching or stripping off a substring). The file extension is\nautomatically taken from the file name of the current buffer. Testbench\nfiles can be created in a different directory by prepending a relative or\nabsolute path to the file name." (cons (regexp :tag "From regexp") (string :tag "To string ")) vhdl-testbench-architecture-file-name #[0 "\207" [vhdl-architecture-file-name] 1 #1#] "Specifies how the testbench architecture file name is obtained.\nThe architecture file name can be obtained by modifying the testbench entity\nand/or architecture name (e.g. attaching or stripping off a substring). The\nstring that is matched against the regexp is the concatenation of the entity\nand the architecture name separated by a space. This gives access to both\nnames (see default setting as example). Testbench files can be created in\na different directory by prepending a relative or absolute path to the file\nname." (cons (regexp :tag "From regexp") (string :tag "To string ")) vhdl-comment "Customizations for comments." vhdl vhdl-self-insert-comments #[0 "\300\207" [t] 1 #1#] "Non-nil means various templates automatically insert help comments." vhdl-prompt-for-comments #[0 "\300\207" [t] 1 #1#] "Non-nil means various templates prompt for user definable comments." vhdl-inline-comment-column #[0 "\300\207" [40] 1 #1#] "Column to indent and align inline comments to.\nOverrides local option `comment-column'.\n\nNOTE: Activate the new setting in a VHDL buffer by using the menu entry\n \"Activate Options\"." integer vhdl-end-comment-column #[0 "\300\207" [79] 1 #1#] "End of comment column.\nComments that exceed this column number are wrapped.\n\nNOTE: Activate the new setting in a VHDL buffer by using the menu entry\n \"Activate Options\"." vhdl-beautify "Customizations for beautification."] 8) (byte-code "\300\301\302\303\304DD\305\306\307\310\311&\210\300\312\302\303\313DD\314\306\307\310\311&\210\300\315\302\303\316DD\317\306\320\310\311&\210\300\321\302\303\322DD\323\306\307\310\311&\210\300\324\302\303\325DD\326\306\327\310\311\330\331& \210\332\333\334\335\310\336%\210\300\337\302\303\340DD\341\306\307\342\343\310\333& \210\300\344\302\303\345DD\346\306\307\342\347\310\333& \210\300\350\302\303\351DD\352\306\307\342\353\310\333& \210\300\354\302\303\355DD\356\306\307\342\357\310\333& \210\300\360\302\303\361DD\362\306\307\342\363\310\333& \210\300\364\302\303\365DD\366\306\307\342\367\310\333& \210\300\370\302\303\371DD\372\306\307\310\333&\210\300\373\302\303\374DD\375\306\376\342\377\310\333& \210\300\201@�\302\303\201A�DD\201B�\306\201C�\342\201D�\310\333& \210\300\201E�\302\303\201F�DD\201G�\306\320\342\201H�\310\333& \210\300\201I�\302\303\201J�DD\201K�\306\201L�\342\201M�\310\333& \210\332\201N�\334\201O�\310\336%\210\300\201P�\302\303\201Q�DD\201R�\306\307\310\201N�&\210\300\201S�\302\303\201T�DD\201U�\306\201V�\310\201N�&\210\300\201W�\302\303\201X�DD\201Y�\306\201Z�\310\201N�&\207" [custom-declare-variable vhdl-auto-align funcall function #[0 "\300\207" [t] 1 #1=""] "Non-nil means align some templates automatically after generation." :type boolean :group vhdl-beautify vhdl-align-groups #[0 "\300\207" [t] 1 #1#] "Non-nil means align groups of code lines separately.\nA group of code lines is a region of consecutive lines between two lines that\nmatch the regexp in option `vhdl-align-group-separate'." vhdl-align-group-separate #[0 "\300\207" ["^\\s-*$"] 1 #1#] "Regexp for matching a line that separates groups of lines for alignment.\nExamples:\n \"^\\s-*$\": matches an empty line\n \"^\\s-*\\(--.*\\)?$\": matches an empty line or a comment-only line" regexp vhdl-align-same-indent #[0 "\300\207" [t] 1 #1#] "Non-nil means align blocks with same indent separately.\nWhen a region or the entire buffer is aligned, the code is divided into\nblocks of same indent which are aligned separately (except for argument/port\nlists). This gives nicer alignment in most cases.\nOption `vhdl-align-groups' still applies within these blocks." vhdl-beautify-options #[0 "\300\207" [(t t t t t)] 1 #1#] "List of options for beautifying code.\nAllows you to disable individual features of code beautification." (list (boolean :tag "Whitespace cleanup ") (boolean :tag "Single statement per line") (boolean :tag "Indentation ") (boolean :tag "Alignment ") (boolean :tag "Case fixing ")) :version "24.4" custom-declare-group vhdl-highlight nil "Customizations for highlighting." vhdl vhdl-highlight-keywords #[0 "\300\207" [t] 1 #1#] "Non-nil means highlight VHDL keywords and other standardized words.\nThe following faces are used:\n `font-lock-keyword-face' : keywords\n `font-lock-type-face' : standardized types\n `vhdl-font-lock-attribute-face': standardized attributes\n `vhdl-font-lock-enumvalue-face': standardized enumeration values\n `vhdl-font-lock-function-face' : standardized function and package names\n\nNOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu\n entry \"Fontify Buffer\")." :set #[514 "\300\301#\207" [vhdl-custom-set vhdl-font-lock-init] 6 "\n\n(fn VARIABLE VALUE)"] vhdl-highlight-names #[0 "\300\207" [t] 1 #1#] "Non-nil means highlight declaration names and construct labels.\nThe following faces are used:\n `font-lock-function-name-face' : names in declarations of units,\n subprograms, components, as well as labels of VHDL constructs\n `font-lock-type-face' : names in type/nature declarations\n `vhdl-font-lock-attribute-face': names in attribute declarations\n `font-lock-variable-name-face' : names in declarations of signals,\n variables, constants, subprogram parameters, generics, and ports\n\nNOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu\n entry \"Fontify Buffer\")." #[514 "\300\301#\207" [vhdl-custom-set vhdl-font-lock-init] 6 "\n\n(fn VARIABLE VALUE)"] vhdl-highlight-special-words #[0 "\300\207" [nil] 1 #1#] "Non-nil means highlight words with special syntax.\nThe words with syntax and color specified in option `vhdl-special-syntax-alist'\nare highlighted accordingly.\nCan be used for visual support of naming conventions.\n\nNOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu\n entry \"Fontify Buffer\")." #[514 "\300\301#\207" [vhdl-custom-set vhdl-font-lock-init] 6 "\n\n(fn VARIABLE VALUE)"] vhdl-highlight-forbidden-words #[0 "\300\207" [nil] 1 #1#] "Non-nil means highlight forbidden words.\nThe reserved words specified in option `vhdl-forbidden-words' or having the\nsyntax specified in option `vhdl-forbidden-syntax' are highlighted in a\nwarning color (face `vhdl-font-lock-reserved-words-face') to indicate not to\nuse them.\n\nNOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu\n entry \"Fontify Buffer\")." #[514 "\300\301\302$\207" [vhdl-custom-set vhdl-words-init vhdl-font-lock-init] 7 "\n\n(fn VARIABLE VALUE)"] vhdl-highlight-verilog-keywords #[0 "\300\207" [nil] 1 #1#] "Non-nil means highlight Verilog keywords as reserved words.\nVerilog keywords are highlighted in a warning color (face\n`vhdl-font-lock-reserved-words-face') to indicate not to use them.\n\nNOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu\n entry \"Fontify Buffer\")." #[514 "\300\301\302$\207" [vhdl-custom-set vhdl-words-init vhdl-font-lock-init] 7 "\n\n(fn VARIABLE VALUE)"] vhdl-highlight-translate-off #[0 "\300\207" [nil] 1 #1#] "Non-nil means background-highlight code excluded from translation.\nThat is, all code between \"-- pragma translate_off\" and\n\"-- pragma translate_on\" is highlighted using a different background color\n(face `vhdl-font-lock-translate-off-face').\nNote: this might slow down on-the-fly fontification (and thus editing).\n\nNOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu\n entry \"Fontify Buffer\")." #[514 "\300\301#\207" [vhdl-custom-set vhdl-font-lock-init] 6 "\n\n(fn VARIABLE VALUE)"] vhdl-highlight-case-sensitive #[0 "\300\207" [nil] 1 #1#] "Non-nil means consider case for highlighting.\nPossible trade-off:\n non-nil also upper-case VHDL words are highlighted, but case of words with\n special syntax is not considered\n nil only lower-case VHDL words are highlighted, but case of words with\n special syntax is considered\nOverrides local option `font-lock-keywords-case-fold-search'.\n\nNOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu\n entry \"Fontify Buffer\")." vhdl-special-syntax-alist #[0 "\300\207" [(("generic/constant" "\\<\\w+_[cg]\\>" "Gold3" "BurlyWood1" nil) ("type" "\\<\\w+_t\\>" "ForestGreen" "PaleGreen" nil) ("variable" "\\<\\w+_v\\>" "Grey50" "Grey80" nil))] 1 #1#] "List of special syntax to be highlighted.\nIf option `vhdl-highlight-special-words' is non-nil, words with the specified\nsyntax (as regular expression) are highlighted in the corresponding color.\n\n Name : string of words and spaces\n Regexp : regular expression describing word syntax\n (e.g., `\\=\\<\\w+_c\\>' matches word with suffix `_c')\n expression must start with `\\=\\<' and end with `\\>'\n if only whole words should be matched (no substrings)\n Color (light): foreground color for light background\n (matching color examples: Gold3, Grey50, LimeGreen, Tomato,\n LightSeaGreen, DodgerBlue, Gold, PaleVioletRed)\n Color (dark) : foreground color for dark background\n (matching color examples: BurlyWood1, Grey80, Green, Coral,\n AquaMarine2, LightSkyBlue1, Yellow, PaleVioletRed1)\n In comments : If non-nil, words are also highlighted inside comments\n\nCan be used for visual support of naming conventions, such as highlighting\ndifferent kinds of signals (e.g. `Clk50', `Rst_n') or objects (e.g.\n`Signal_s', `Variable_v', `Constant_c') by distinguishing them using\ncommon substrings or name suffices.\nFor each entry, a new face is generated with the specified colors and name\n`vhdl-font-lock-' + name + `-face'.\n\nNOTE: Activate a changed regexp in a VHDL buffer by re-fontifying it (menu\n entry `Fontify Buffer'). All other changes require restarting Emacs." (repeat (list :tag "Face" :indent 2 (string :tag "Name ") (regexp :tag "Regexp " "\\w+_") (string :tag "Color (light)") (string :tag "Color (dark) ") (boolean :tag "In comments "))) #[514 "\300\301#\207" [vhdl-custom-set vhdl-font-lock-init] 6 "\n\n(fn VARIABLE VALUE)"] vhdl-forbidden-words #[0 "\300\207" [nil] 1 #1#] "List of forbidden words to be highlighted.\nIf option `vhdl-highlight-forbidden-words' is non-nil, these reserved\nwords are highlighted in a warning color to indicate not to use them.\n\nNOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu\n entry \"Fontify Buffer\")." (repeat (string :format "%v")) #[514 "\300\301\302$\207" [vhdl-custom-set vhdl-words-init vhdl-font-lock-init] 7 "\n\n(fn VARIABLE VALUE)"] vhdl-forbidden-syntax #[0 "\300\207" [#1#] 1 #1#] "Syntax of forbidden words to be highlighted.\nIf option `vhdl-highlight-forbidden-words' is non-nil, words with this\nsyntax are highlighted in a warning color to indicate not to use them.\nCan be used to highlight too long identifiers (e.g. \"\\w\\w\\w\\w\\w\\w\\w\\w\\w\\w+\"\nhighlights identifiers with 10 or more characters).\n\nNOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu\n entry \"Fontify Buffer\")." #[514 "\300\301\302$\207" [vhdl-custom-set vhdl-words-init vhdl-font-lock-init] 7 "\n\n(fn VARIABLE VALUE)"] vhdl-directive-keywords #[0 "\300\207" [("psl" "pragma" "synopsys")] 1 #1#] "List of compiler directive keywords recognized for highlighting.\n\nNOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu\n entry \"Fontify Buffer\")." (repeat (string :format "%v")) #[514 "\300\301\302$\207" [vhdl-custom-set vhdl-words-init vhdl-font-lock-init] 7 "\n\n(fn VARIABLE VALUE)"] vhdl-speedbar "Customizations for speedbar." vhdl-speedbar-auto-open #[0 "\300\207" [nil] 1 #1#] "Non-nil means automatically open speedbar at startup.\nAlternatively, the speedbar can be opened from the VHDL menu." vhdl-speedbar-display-mode #[0 "\300\207" [files] 1 #1#] "Specifies the default displaying mode when opening speedbar.\nAlternatively, the displaying mode can be selected from the speedbar menu or\nby typing `f' (files), `h' (directory hierarchy) or `H' (project hierarchy)." (choice (const :tag "Files" files) (const :tag "Directory hierarchy" directory) (const :tag "Project hierarchy" project)) vhdl-speedbar-scan-limit #[0 "\300\207" [(10000000 (1000000 50))] 1 #1#] "Limits scanning of large files and netlists.\nDesign units: maximum file size to scan for design units\nHierarchy (instances of subcomponents):\n File size: maximum file size to scan for instances (in bytes)\n Instances per arch: maximum number of instances to scan per architecture\n\n\"None\" always means that there is no limit.\nIn case of files not or incompletely scanned, a warning message and the file\nnames are printed out.\nBackground: scanning for instances is considerably slower than scanning for\ndesign units, especially when there are many instances. These limits should\nprevent the scanning of large netlists." (list (choice :tag "Design units" :format "%t : %[Value Menu%] %v" (const :tag "None" nil) (integer :tag "File size")) (list :tag "Hierarchy" :indent 2 (choice :tag "File size" :format "%t : %[Value Menu%] %v" (const :tag "None" nil) (integer :tag "Size ")) (choice :tag "Instances per arch" (const :tag "None" nil) (integer :tag "Number "))))] 10) (byte-code "\300\301\302\303\304DD\305\306\307\310\311&\210\300\312\302\303\313DD\314\306\307\310\311&\210\300\315\302\303\316DD\317\306\320\310\311&\210\300\321\302\303\322DD\323\306\324\310\311&\210\325\326\327\330\310\331%\210\300\332\302\303\333DD\334\306\307\310\326&\210\300\335\302\303\336DD\337\306\307\310\326&\210\300\340\302\303\341DD\342\306\307\310\326&\210\300\343\302\303\344DD\345\306\307\310\326&\210\325\346\327\347\310\331%\210\300\350\302\303\351DD\352\306\307\310\346&\210\300\353\302\303\354DD\355\306\307\310\346&\210\325\356\327\357\310\331%\210\300\360\302\303\361DD\362\306\307\310\356&\210\300\363\302\303\364DD\365\306\307\310\356&\210\300\366\302\303\367DD\370\306\307\371\372\310\356& \210\300\373\302\303\374DD\375\306\307\310\356&\210\300\376\302\303\377DD\201@�\306\307\310\356&\210\300\201A�\302\303\201B�DD\201C�\306\307\310\356&\210\201D�\201A�\201E�\201F�#\210\325\201G�\327\201H�\310\331%\210\201I�\201G�\201J�\201K�#\210\201I�\201G�\201L�\201K�#\210\201I�\201G�\201M�\201K�#\210\201I�\201G�\201N�\201K�#\210\201I�\201G�\201O�\201P�#\210\201I�\201G�\201Q�\201P�#\210\201I�\201G�\201R�\201P�#\207" [custom-declare-variable vhdl-speedbar-jump-to-unit funcall function #[0 "\300\207" [t] 1 #1=""] "Non-nil means jump to the design unit code when opened in a buffer.\nThe buffer cursor position is left unchanged otherwise." :type boolean :group vhdl-speedbar vhdl-speedbar-update-on-saving #[0 "\300\207" [t] 1 #1#] "Automatically update design hierarchy when buffer is saved." vhdl-speedbar-save-cache #[0 "\300\207" [(hierarchy display)] 1 #1#] "Automatically save modified hierarchy caches when exiting Emacs.\n Hierarchy: design hierarchy information\n Display: displaying information (which design units to expand)" (set (const :tag "Hierarchy" hierarchy) (const :tag "Display" display)) vhdl-speedbar-cache-file-name #[0 "\300\207" [".emacs-vhdl-cache-\\1-\\2"] 1 #1#] "Name of file for saving hierarchy cache.\n\"\\1\" is replaced by the project name if a project is specified,\n\"directory\" otherwise. \"\\2\" is replaced by the user name (allows for\ndifferent users to have cache files in the same directory). Can also have\nan absolute path (i.e. all caches can be stored in one global directory)." string custom-declare-group vhdl-menu nil "Customizations for menus." vhdl vhdl-index-menu #[0 "\300\207" [nil] 1 #1#] "Non-nil means add an index menu for a source file when loading.\nAlternatively, the speedbar can be used. Note that the index menu scans a file\nwhen it is opened, while speedbar only scans the file upon request." vhdl-source-file-menu #[0 "\300\207" [nil] 1 #1#] "Non-nil means add a menu of all source files in current directory.\nAlternatively, the speedbar can be used." vhdl-hideshow-menu #[0 "\300\207" [nil] 1 #1#] "Non-nil means add hideshow menu and functionality at startup.\nHideshow can also be enabled from the VHDL Mode menu.\nHideshow allows hiding code of various VHDL constructs.\n\nNOTE: Activate the new setting in a VHDL buffer by using the menu entry\n \"Activate Options\"." vhdl-hide-all-init #[0 "\300\207" [nil] 1 #1#] "Non-nil means hide all design units initially after a file is loaded." vhdl-print "Customizations for printing." vhdl-print-two-column #[0 "\300\207" [t] 1 #1#] "Non-nil means print code in two columns and landscape format.\nAdjusts settings in a way that PostScript printing (\"File\" menu, `ps-print')\nprints VHDL files in a nice two-column landscape style.\n\nNOTE: Activate the new setting by restarting Emacs.\n Overrides `ps-print' settings locally." vhdl-print-customize-faces #[0 "\300\207" [t] 1 #1#] "Non-nil means use an optimized set of faces for PostScript printing.\n\nNOTE: Activate the new setting by restarting Emacs.\n Overrides `ps-print' settings locally." vhdl-misc "Miscellaneous customizations." vhdl-intelligent-tab #[0 "\300\207" [t] 1 #1#] "Non-nil means `TAB' does indentation, word completion and tab insertion.\nThat is, if preceding character is part of a word then complete word,\nelse if not at beginning of line then insert tab,\nelse if last command was a `TAB' or `RET' then dedent one step,\nelse indent current line (i.e. `TAB' is bound to `vhdl-electric-tab').\nIf nil, TAB always indents current line (i.e. `TAB' is bound to\n`indent-according-to-mode').\n\nNOTE: Activate the new setting in a VHDL buffer by using the menu entry\n \"Activate Options\"." vhdl-indent-syntax-based #[0 "\300\207" [t] 1 #1#] "Non-nil means indent lines of code based on their syntactic context.\nOtherwise, a line is indented like the previous nonblank line. This can be\nuseful in large files where syntax-based indentation gets very slow." vhdl-indent-comment-like-next-code-line #[0 "\300\207" [t] 1 #1#] "Non-nil means comment lines are indented like the following code line.\nOtherwise, comment lines are indented like the preceding code line.\nIndenting comment lines like the following code line gives nicer indentation\nwhen comments precede the code that they refer to." :version "24.3" vhdl-word-completion-case-sensitive #[0 "\300\207" [nil] 1 #1#] "Non-nil means word completion using `TAB' is case sensitive.\nThat is, `TAB' completes words that start with the same letters and case.\nOtherwise, case is ignored." vhdl-word-completion-in-minibuffer #[0 "\300\207" [t] 1 #1#] "Non-nil enables word completion in minibuffer (for template prompts).\n\nNOTE: Activate the new setting by restarting Emacs." vhdl-underscore-is-part-of-word #[0 "\300\207" [nil] 1 #1#] "Non-nil means consider the underscore character `_' as part of word.\nAn identifier containing underscores is then treated as a single word in\nselect and move operations. All parts of an identifier separated by underscore\nare treated as single words otherwise." make-obsolete-variable superword-mode "24.4" vhdl-related "Related general customizations." custom-add-to-group hideshow custom-group paren-showing ps-print speedbar comment-style custom-variable line-number-mode transient-mark-mode] 10) (byte-code "\300\301\302\303#\210\300\301\304\303#\207" [custom-add-to-group vhdl-related user-full-name custom-variable user-mail-address] 4)#@71 If non-nil, use absolute instead of relative path for compiled files. (defvar vhdl-compile-absolute-path nil (#$ . 74768))#@43 Character to use in comment display line. (defvar vhdl-comment-display-line-char 45 (#$ . 74896))#@73 Specifies the maximum size of a menu before splitting it into submenus. (defvar vhdl-menu-max-size 20 (#$ . 74999))#@203 Interval used to update progress status during long operations. If a number, percentage complete gets updated after each interval of that many seconds. To inhibit all messages, set this option to nil. (defvar vhdl-progress-interval 1 (#$ . 75121))#@55 If non-nil, inhibits start up compatibility warnings. (defvar vhdl-inhibit-startup-warnings-p nil (#$ . 75375))#@257 If non-nil, all syntactic symbols must be found in `vhdl-offsets-alist'. If the syntactic symbol for a particular line does not match a symbol in the offsets alist, an error is generated, otherwise no error is reported and the syntactic symbol is ignored. (defvar vhdl-strict-syntax-p nil (#$ . 75493))#@65 If non-nil, syntactic info is echoed when the line is indented. (defvar vhdl-echo-syntactic-information-p nil (#$ . 75801))#@143 Default settings for offsets of syntactic elements. Do not change this constant! See the variable `vhdl-offsets-alist' for more information. (defconst vhdl-offsets-alist-default '((string . -1000) (cpp-macro . -1000) (block-open . 0) (block-close . 0) (statement . 0) (statement-cont . vhdl-lineup-statement-cont) (statement-block-intro . +) (statement-case-intro . +) (case-alternative . +) (comment . vhdl-lineup-comment) (arglist-intro . +) (arglist-cont . 0) (arglist-cont-nonempty . vhdl-lineup-arglist) (arglist-close . vhdl-lineup-arglist) (entity . 0) (configuration . 0) (package . 0) (architecture . 0) (package-body . 0) (context . 0) (directive . 0)) (#$ . 75931))#@3208 Association list of syntactic element symbols and indentation offsets. As described below, each cons cell in this list has the form: (SYNTACTIC-SYMBOL . OFFSET) When a line is indented, `vhdl-mode' first determines the syntactic context of the line by generating a list of symbols called syntactic elements. This list can contain more than one syntactic element and the global variable `vhdl-syntactic-context' contains the context list for the line being indented. Each element in this list is actually a cons cell of the syntactic symbol and a buffer position. This buffer position is call the relative indent point for the line. Some syntactic symbols may not have a relative indent point associated with them. After the syntactic context list for a line is generated, `vhdl-mode' calculates the absolute indentation for the line by looking at each syntactic element in the list. First, it compares the syntactic element against the SYNTACTIC-SYMBOL's in `vhdl-offsets-alist'. When it finds a match, it adds the OFFSET to the column of the relative indent point. The sum of this calculation for each element in the syntactic list is the absolute offset for line being indented. If the syntactic element does not match any in the `vhdl-offsets-alist', an error is generated if `vhdl-strict-syntax-p' is non-nil, otherwise the element is ignored. Actually, OFFSET can be an integer, a function, a variable, or one of the following symbols: `+', `-', `++', or `--'. These latter designate positive or negative multiples of `vhdl-basic-offset', respectively: *1, *-1, *2, and *-2. If OFFSET is a function, it is called with a single argument containing the cons of the syntactic element symbol and the relative indent point. The function should return an integer offset. Here is the current list of valid syntactic element symbols: string -- inside multi-line string block-open -- statement block open block-close -- statement block close statement -- a VHDL statement statement-cont -- a continuation of a VHDL statement statement-block-intro -- the first line in a new statement block statement-case-intro -- the first line in a case alternative block case-alternative -- a case statement alternative clause comment -- a line containing only a comment arglist-intro -- the first line in an argument list arglist-cont -- subsequent argument list lines when no arguments follow on the same line as the arglist opening paren arglist-cont-nonempty -- subsequent argument list lines when at least one argument follows on the same line as the arglist opening paren arglist-close -- the solo close paren of an argument list entity -- inside an entity declaration configuration -- inside a configuration declaration package -- inside a package declaration architecture -- inside an architecture body package-body -- inside a package body context -- inside a context declaration (defvar vhdl-offsets-alist (copy-alist vhdl-offsets-alist-default) (#$ . 76616))#@412 Extra offset for line which contains only the start of a comment. Can contain an integer or a cons cell of the form: (NON-ANCHORED-OFFSET . ANCHORED-OFFSET) Where NON-ANCHORED-OFFSET is the amount of offset given to non-column-zero anchored comment-only lines, and ANCHORED-OFFSET is the amount of offset to give column-zero anchored comment-only lines. Just an integer as value is equivalent to (<val> . 0) (defvar vhdl-comment-only-line-offset 0 (#$ . 79910))#@116 Hook for user defined special indentation adjustments. This hook gets called after a line is indented by the mode. (defvar vhdl-special-indent-hook nil (#$ . 80381))#@683 Styles of Indentation. Elements of this alist are of the form: (STYLE-STRING (VARIABLE . VALUE) [(VARIABLE . VALUE) ...]) where STYLE-STRING is a short descriptive string used to select a style, VARIABLE is any `vhdl-mode' variable, and VALUE is the intended value for that variable when using the selected style. There is one special case when VARIABLE is `vhdl-offsets-alist'. In this case, the VALUE is a list containing elements of the form: (SYNTACTIC-SYMBOL . VALUE) as described in `vhdl-offsets-alist'. These are passed directly to `vhdl-set-offset' so there is no need to set every syntactic symbol in your style, only those that are different from the default. (defvar vhdl-style-alist '(("IEEE" (vhdl-basic-offset . 4) (vhdl-offsets-alist))) (#$ . 80553)) (byte-code "\301\302\"\204�\303\302\304\305\"B\211B\266\301\207" [vhdl-style-alist assoc "Default" (vhdl-inhibit-startup-warnings-p vhdl-strict-syntax-p vhdl-echo-syntactic-information-p vhdl-basic-offset vhdl-offsets-alist vhdl-comment-only-line-offset) mapcar #[257 "\211JB\207" [] 3 "\n\n(fn VAR)"]] 5)#@29 Hook called by `vhdl-mode'. (defvar vhdl-mode-hook nil (#$ . 81649)) (byte-code "\301\302!\210\303W\203�\301\304!\210\301\305!\207" [emacs-major-version require compile 28 easymenu hippie-exp] 2)#@376 Insert a key-value pair into an alist. The alist is referenced by ALIST-SYMBOL. The key-value pair is made from KEY and VALUE. If the key-value pair referenced by KEY can be found in the alist, the value of KEY will be set to VALUE. If the key-value pair cannot be found in the alist, it will be inserted into the head of the alist. (fn ALIST-SYMBOL KEY &optional VALUE) (defalias 'vhdl-aput #[770 "J\300\"\211\203�\211\241\207BBL\207" [assoc] 8 (#$ . 81853)])#@155 Delete a key-value pair from the alist. Alist is referenced by ALIST-SYMBOL and the key-value pair to remove is pair matching KEY. (fn ALIST-SYMBOL KEY) (defalias 'vhdl-adelete #[514 "J\300@@\232\203�A\262L\210\202�A\211\262\2054�@@\232\203.�A\241\210\202�\211\262\202�\207" [nil] 6 (#$ . 82333)])#@115 Return the value in ALIST that is associated with KEY. If KEY is not found, then nil is returned. (fn ALIST KEY) (defalias 'vhdl-aget #[514 "\300\"A\207" [assoc] 5 (#$ . 82656)])#@108 Do whatever is necessary to keep the region active in XEmacs. Ignore byte-compiler warnings you might see. (defalias 'vhdl-keep-region-active #[0 "\300\207" [nil] 1 (#$ . 82844)]) (byte-code "\300\301!\204 �\302\301\303\"\210\300\304!\204�\302\304\305\"\210\300\306!\204!�\302\306\307\"\210\300\310!\204,�\302\310\311\"\210\300\312!\2047�\302\312\313\"\210\300\314!\204B�\302\314\315\"\210\316\317\320\"\207" [fboundp wildcard-to-regexp defalias #[257 "\300\301\"\302OG\2034�W\2034�H\303\267\202&�\304\202)�\305\202)�\306!P\262T\262\210\202�\307\310Q\207" [string-match "[*?]" 0 #s(hash-table size 2 test eq rehash-size 1.5 rehash-threshold 0.8125 purecopy t data (42 30 63 34)) "[^�]*" "[^�]" char-to-string "\\`" "\\'"] 8 "Simplified version of `wildcard-to-regexp' from Emacs's `files.el'.\n\n(fn WILDCARD)"] regexp-opt #[513 "\211\203�\300\202 �\301\203�\302\202�\301\303\304\305#Q\207" ["\\(" "" "\\)" mapconcat regexp-quote "\\|"] 9 "\n\n(fn STRINGS &optional PAREN)"] match-string-no-properties match-string subst-char-in-string #[1027 "G\203\n�\202 �\300!\301V\203)�S\262\211H=\203 �\211I\210\202 �\207" [copy-sequence 0] 9 "\n\n(fn FROMCHAR TOCHAR STRING &optional INPLACE)"] file-expand-wildcards #[513 "\300!\301!\211\203�\302\303\"\203�\304\305\306\307!!\"\202�\211CC\310\242\203m�\242@\2035�\311\307\242@!!\203d�\312\310\304\313\314\242@\206B�\315\n\316 !#\"\"\242@\203_�\204_�\304\317\320\"\"\202`�\211\244\266\202\211\242A\240\210\202 �\207" [file-name-nondirectory file-name-directory string-match "[[*?]" mapcar file-name-as-directory file-expand-wildcards directory-file-name nil file-directory-p delq #[257 "\300\301\302!\"?\205 �\211\207" [string-match "\\`\\.\\.?\\'" file-name-nondirectory] 5 "\n\n(fn NAME)"] directory-files "." wildcard-to-regexp make-closure #[257 "\300\242@P\207" [V0] 3 "\n\n(fn NAME)"]] 15 "Taken from Emacs's `files.el'.\n\n(fn PATTERN &optional FULL)"] member-ignore-case member defvaralias vhdl-last-input-event last-input-event] 3)#@44 Warnings to tell the user during start up. (defvar vhdl-warnings nil (#$ . 84891))#@64 Wait until idle, then run FUNCTION. (fn SECS REPEAT FUNCTION) (defalias 'vhdl-run-when-idle #[771 "\300\301!\203�\301\302\303%\207\304#\305\306I\207" [fboundp start-itimer "vhdl-mode" t run-with-idle-timer 0 nil] 9 (#$ . 84979)])#@75 Wait until idle, then print out warning STRING and beep. (fn &rest ARGS) (defalias 'vhdl-warning-when-idle #[128 "\302\303\"\203 �\304\305\"\207 \204�\306\307\310\311#\210\211 B\211\207" [noninteractive vhdl-warnings apply format-message vhdl-warning t vhdl-run-when-idle 0.1 nil vhdl-print-warnings] 6 (#$ . 85222)])#@66 Print out warning STRING and beep. (fn STRING &optional NOBEEP) (defalias 'vhdl-warning #[513 "\301\302\"\210\211\206\n�?\205�\303 \207" [noninteractive message "WARNING: %s" beep] 5 (#$ . 85551)])#@49 Print out messages in variable `vhdl-warnings'. (defalias 'vhdl-print-warnings #[0 "G\237\211\203�\301\302@\"\210A\211\204 �\303 \210\211\304V\205\"�\301\305!\207" [vhdl-warnings message "WARNING: %s" beep 1 "WARNING: See warnings in message buffer (type `C-c M-m')."] 5 (#$ . 85759)]) (byte-code ";\204 �\305\306\307!\210 <\204�\310\306\311!\210\n@G\312U\203>�\n\313\2034�\314@\315\"B\262A\262\202 �\211\237\266\316\302\n\"\210 @G\312U\203f� \313\203\\�\314@\317\"B\262A\262\202H�\211\237\266\316\303 \"\210 @G\320U\203\241� \313\211\203\230�@\262\211@A@\321\3228\313\323\324\325\326\312\n8\257\nB\262A\262\202q�\237\266\306\327!\210 @G\330U\203\307� \211\203\301�\312@\233\321\320@\233B\241\210\211A\262\202\252�\210\316\303 \"\210\f@G\331U\203\f\313\211\203 @\262\211@A@\321\332\3128\321\232?\205\355�\3128\3208\325\326@\227\333\n8\334 8\313\257\fB\262A\262\202\322�\237\266\306\335!\210\f@G\336U\203<\f\211\2036\320@\233\337\333@\233B\241\210\211A\262\202\210\316\304\f\"\210\f@G\340U\203b\f\211\203\\\312@\233\321\320@\233B\241\210\211A\262\202E\210\316\304\f\"\210\313\207" [vhdl-compiler vhdl-standard vhdl-model-alist vhdl-project-alist vhdl-compiler-alist "ModelSim" vhdl-warning-when-idle "Option `vhdl-compiler' has changed format; customize again" (87 nil) "Option `vhdl-standard' has changed format; customize again" 3 nil append (#1="") customize-save-variable (#1#) 4 #1# 2 "./" "work" "work/" "Makefile" "Option `vhdl-project-alist' changed format; please re-customize" 10 7 "make -f \\1" 5 6 "Option `vhdl-compiler-alist' changed; please reset and re-customize" 12 "mkdir \\1" 13] 15) (byte-code "\304@8G\305U\203%�\211\203�\304@8AA\306\241\210\211A\262\202 �\210\307\300\"\210 \310\232\2032�\311\307\301 \"\210\n;\203?�\nC\307\302\n\"\210\312\303!\204M�\313\303\314\"\210\202U�\303\315N\204U�\314\311\207" [vhdl-compiler-alist vhdl-project vhdl-project-file-name speedbar-indentation-width 11 3 (0) customize-save-variable "" nil boundp defvar-1 2 saved-value] 3)#@65 Check if STANDARD is specified as used standard. (fn STANDARD) (defalias 'vhdl-standard-p #[257 "\211@=\206\f�\211A@>\207" [vhdl-standard] 3 (#$ . 87835)])#@108 Return non-nil if a project is displayed, i.e. directories or files are specified. (fn &optional WARNING) (defalias 'vhdl-project-p #[256 "\302 \"\203 �\207\203�\211\203�\303\304\"\210\305\207" [vhdl-project vhdl-project-alist assoc vhdl-warning-when-idle "Project does not exist: \"%s\"" nil] 4 (#$ . 88000)])#@55 Resolve environment variables in STRING. (fn STRING) (defalias 'vhdl-resolve-env-variable #[257 "\300\301\"\203�\302\303\"\304\302\305\"!\302\306\"Q\262\202��\207" [string-match "\\(.*\\)\\${?\\(\\(\\w\\|_\\)+\\)}?\\(.*\\)" match-string 1 getenv 2 4] 6 (#$ . 88323)])#@118 Return the default directory of the current project or the directory of the current buffer if no project is defined. (defalias 'vhdl-default-directory #[0 "\303 \203�\304\305\306 \"A@!!\207\n\207" [vhdl-project-alist vhdl-project default-directory vhdl-project-p expand-file-name vhdl-resolve-env-variable vhdl-aget] 5 (#$ . 88604)])#@187 Enable case insensitive search and switch to syntax table that includes `_', then execute BODY, and finally restore the old environment. Used for consistent searching. (fn &rest BODY) (defalias 'vhdl-prepare-search-1 '(macro . #[128 "\300\301\302\303BBE\207" [let ((case-fold-search t)) with-syntax-table vhdl-mode-ext-syntax-table] 6 (#$ . 88946)])) (put 'vhdl-prepare-search-1 'edebug-form-spec t)#@183 Enable case insensitive search, switch to syntax table that includes `_', then execute BODY, and finally restore the old environment. Used for consistent searching. (fn &rest BODY) (defalias 'vhdl-prepare-search-2 '(macro . #[128 "\300\301\302\303\304BEE\207" [let ((case-fold-search t)) with-syntax-table vhdl-mode-ext-syntax-table progn] 7 (#$ . 89355)])) (put 'vhdl-prepare-search-2 'edebug-form-spec t)#@79 Visit file FILE-NAME and execute BODY. (fn FILE-NAME ISSUE-ERROR &rest BODY) (defalias 'vhdl-visit-file '(macro . #[642 "\300\301\302BBF\207" [vhdl--visit-file lambda nil] 9 (#$ . 89769)])) (byte-code "\300\301\302\303#\210\304\301\305\306#\300\207" [put vhdl-visit-file edebug-form-spec t function-put lisp-indent-function 2] 4)#@39 (fn FILE-NAME ISSUE-ERROR BODY-FUN) (defalias 'vhdl--visit-file #[771 "\204�\211 \207\300!?\205\256�p\301!\302\203�q\204y�\3031T�\304!q\210\305\262\306!\210\307\310 !\311\312\313#\210\311\314\315#\210\311\316\315#\210\311\317\320#\210\321!\266\3050\202v�\210\203l�\211\203a�\322p!\210q\210\323\324\"\202v�\325\326\327\"\305\"\210\302\203\242�\3301\204� 0\210\202\242�\203\233�\203\220�\322p!\210q\210\323A@!\202\240�\325A@!\266\211\203\252�\322p!\210q\266\203\207" [file-directory-p find-buffer-visiting nil (error) create-file-buffer t vhdl-insert-file-contents copy-syntax-table syntax-table modify-syntax-entry 45 ". 12" 10 ">" 13 95 "w" set-syntax-table kill-buffer error "ERROR: File cannot be opened: \"%s\"" vhdl-warning format "File cannot be opened: \"%s\"" (error)] 11 (#$ . 90108)])#@98 Nicked from `insert-file-contents-literally', but allow coding system conversion. (fn FILENAME) (defalias 'vhdl-insert-file-contents #[257 "\303\211\211\304\305\"+\207" [jka-compr-compression-info-list after-insert-file-functions format-alist nil insert-file-contents t] 4 (#$ . 90942)])#@25 Sort ALIST. (fn ALIST) (defalias 'vhdl-sort-alist #[257 "\300\301\"\207" [sort #[514 "@@\231\207" [] 4 "\n\n(fn A B)"]] 4 (#$ . 91240)])#@62 Recursively get subdirectories of DIRECTORY. (fn DIRECTORY) (defalias 'vhdl-get-subdirs #[257 "\300!C\301\302\303\304#\262\211\203'�\305@!\203 �\306\307@!\"\262\211A\262\202\f�\207" [file-name-as-directory nil vhdl-directory-files t "\\w.*" file-directory-p append vhdl-get-subdirs] 7 (#$ . 91386)])#@94 As `aput', but delete key-value pair if VALUE is nil. (fn ALIST-SYMBOL KEY &optional VALUE) (defalias 'vhdl-aput-delete-if-nil #[770 "\211\203\n�\300#\207\301\"\207" [vhdl-aput vhdl-adelete] 7 (#$ . 91701)])#@87 Delete by side effect the first occurrence of ELT as a member of LIST. (fn ELT LIST) (defalias 'vhdl-delete #[514 "\300B\262\211\211A\203�A@\232\204�\211A\262\202�\203$�\211AA\241\210\210\211A\207" [nil] 5 (#$ . 91920)])#@65 Refresh directory or project with name KEY. (fn &optional KEY) (defalias 'vhdl-speedbar-refresh #[256 "\301\300!\205A�\302!\205A�\303 \204�\304 \202?�\305!\210\212eb\210\306\307\310Q\311\312#)\203<�\313\225b\210\314 \210\315u\210\314 \210\316\317!\210\305!\262\207" [speedbar-frame boundp frame-live-p selected-frame speedbar-refresh select-frame re-search-forward "^\\([0-9]+:\\s-*<\\)->\\s-+" "$" nil t 1 speedbar-do-function-pointer -2 message "Refreshing speedbar...done"] 6 (#$ . 92157)])#@48 Get *Messages* buffer to show recent messages. (defalias 'vhdl-show-messages #[0 "\300\301!\207" [display-buffer "*Messages*"] 2 (#$ . 92664) nil])#@46 Return whether direct instantiation is used. (defalias 'vhdl-use-direct-instantiation #[0 "\301=\206�\302=\205�\303\304!?\207" [vhdl-use-direct-instantiation always standard vhdl-standard-p 87] 2 (#$ . 92817)])#@45 Return larger marker. (fn MARKER1 MARKER2) (defalias 'vhdl-max-marker #[514 "V\203�\207\207" [] 4 (#$ . 93037)])#@49 Goto marker in appropriate buffer. (fn MARKER) (defalias 'vhdl-goto-marker #[257 "\300!\203 �\301!q\210\211b\207" [markerp marker-buffer] 3 (#$ . 93160)])#@103 Split menu LIST into several submenus, if number of elements > `vhdl-menu-max-size'. (fn LIST TITLE) (defalias 'vhdl-menu-split #[514 "GV\203R�\301\211\302\303\203>�@B\262A\262\211T\262\211U\203\f�\304\305#\237BB\262\303\262T\262\301\262\202\f�\203O�\304\305#\237BB\262\237\207\207" [vhdl-menu-max-size nil 1 0 format "%s %s"] 11 (#$ . 93324)])#@28 Keymap for VHDL templates. (defvar vhdl-template-map nil (#$ . 93705))#@33 Initialize `vhdl-template-map'. (defalias 'vhdl-template-map-init #[0 "\301 \302\303\304#\210\302\305\306#\210\302\307\310#\210\302\311\312#\210\302\313\314#\210\302\315\316#\210\302\317\320#\210\302\321\322#\210\302\323\324#\210\302\325\326#\210\302\327\330#\210\302\331\332#\210\302\333\334#\210\302\335\336#\210\302\337\340#\210\302\341\342#\210\302\343\344#\210\302\345\346#\210\302\347\350#\210\302\351\352#\210\302\353\354#\210\302\355\356#\210\302\357\360#\210\302\361\362#\210\302\363\364#\210\302\365\366#\210\302\367\370#\210\302\371\372#\210\302\373\374#\210\302\375\376#\210\302\377\201@�#\210\302\201A�\201B�#\210\302\201C�\201D�#\210\302\201E�\201F�#\210\302\201G�\201H�#\210\302\201I�\201J�#\210\302\201K�\201L�#\210\302\201M�\300#\210\302\201N�\201O�#\210\302\201P�\201Q�#\210\302\201R�\201S�#\210\302\201T�\201U�#\210\302\201V�\201W�#\210\302\201X�\201Y�#\210\302\201Z�\201[�#\210\302\201\\�\201]�#\210\302\201^�\201_�#\210\302\201`�\201a�#\210\302\201b�\201c�#\210\302\201d�\201e�#\210\302\201f�\201g�#\210\302\201h�\201i�#\210\302\201j�\201k�#\210\302\201l�\201m�#\210\302\201n�\201o�#\210\302\201p�\201q�#\210\302\201r�\201s�#\210\302\201t�\201u�#\210\302\201v�\201w�#\210\302\201x�\201y�#\210\302\201z�\201{�#\210\302\201|�\201}�#\210\302\201~�\201�#\210\302\201\200�\201\201�#\210\302\201\202�\201\203�#\210\302\201\204�\201\205�#\210\302\201\206�\201\207�#\210\302\201\210�\201\211�#\210\302\201\212�\201\213�#\210\302\201\214�\201\215�#\210\302\201\216�\201\217�#\210\302\201\220�\201\221�#\210\302\201\222�\201\223�#\210\302\201\224�\201\225�#\210\201\226�\201\227�!\203\343\302\201\230�\201\231�#\210\302\201\232�\201\233�#\210\302\201\234�\201\235�#\210\302\201\236�\201\237�#\210\302\201\240�\201\241�#\210\302\201\242�\201\243�#\210\302\201\244�\201\245�#\210\302\201\246�\201\247�#\210\302\201\250�\201\251�#\210\302\201\252�\201\253�#\210\302\201\254�\201\255�#\210\201\226�\201\256�!\205�\302\201\257�\201\260�#\210\302\201\261�\201\262�#\207" [vhdl-template-map make-sparse-keymap define-key "al" vhdl-template-alias "ar" vhdl-template-architecture "at" vhdl-template-assert "ad" vhdl-template-attribute-decl "as" vhdl-template-attribute-spec "bl" vhdl-template-block "ca" vhdl-template-case-is "cd" vhdl-template-component-decl "ci" vhdl-template-component-inst "cs" vhdl-template-conditional-signal-asst "Cb" vhdl-template-block-configuration "Cc" vhdl-template-component-conf "Cd" vhdl-template-configuration-decl "Cs" vhdl-template-configuration-spec "co" vhdl-template-constant "ct" vhdl-template-context "di" vhdl-template-disconnect "el" vhdl-template-else "ei" vhdl-template-elsif "en" vhdl-template-entity "ex" vhdl-template-exit "fi" vhdl-template-file "fg" vhdl-template-for-generate "fl" vhdl-template-for-loop "" vhdl-template-footer "fb" vhdl-template-function-body "fd" vhdl-template-function-decl "ge" vhdl-template-generic "gd" vhdl-template-group-decl "gt" vhdl-template-group-template "" vhdl-template-header "ig" vhdl-template-if-generate "it" vhdl-template-if-then "li" vhdl-template-library "lo" vhdl-template-bare-loop " " vhdl-template-modify "" vhdl-template-insert-date "ma" "ne" vhdl-template-next "ot" vhdl-template-others "Pd" vhdl-template-package-decl "Pb" vhdl-template-package-body "(" vhdl-template-paired-parens "po" vhdl-template-port "pb" vhdl-template-procedure-body "pd" vhdl-template-procedure-decl "pc" vhdl-template-process-comb "ps" vhdl-template-process-seq "rp" vhdl-template-report "rt" vhdl-template-return "ss" vhdl-template-selected-signal-asst "si" vhdl-template-signal "su" vhdl-template-subtype "ty" vhdl-template-type "us" vhdl-template-use "va" vhdl-template-variable "wa" vhdl-template-wait "wl" vhdl-template-while-loop "wi" vhdl-template-with "wc" vhdl-template-clocked-wait "b" vhdl-template-package-numeric-bit "n" vhdl-template-package-numeric-std "s" vhdl-template-package-std-logic-1164 "A" vhdl-template-package-std-logic-arith "M" vhdl-template-package-std-logic-misc "S" vhdl-template-package-std-logic-signed "T" vhdl-template-package-std-logic-textio "U" vhdl-template-package-std-logic-unsigned "t" vhdl-template-package-textio "n" vhdl-template-directive-translate-on "f" vhdl-template-directive-translate-off "N" vhdl-template-directive-synthesis-on "F" vhdl-template-directive-synthesis-off "" vhdl-template-search-prompt vhdl-standard-p ams "br" vhdl-template-break "cu" vhdl-template-case-use "iu" vhdl-template-if-use "lm" vhdl-template-limit "na" vhdl-template-nature "pa" vhdl-template-procedural "qf" vhdl-template-quantity-free "qb" vhdl-template-quantity-branch "qs" vhdl-template-quantity-source "sn" vhdl-template-subnature "te" vhdl-template-terminal math "c" vhdl-template-package-math-complex "r" vhdl-template-package-math-real] 4 (#$ . 93781)]) (vhdl-template-map-init)#@215 Generate a Lisp function name. PREFIX, STRING and optional POSTFIX are concatenated by `-' and spaces in STRING are replaced by `-' and substrings are converted to lower case. (fn PREFIX STRING &optional POSTFIX) (defalias 'vhdl-function-name #[770 "\300\301\"\203�\211\302\303\304\225O\227Q\262\305\224\306O\262\202�\203'�\211\302Q\262\307!\207" [string-match "\\(\\w+\\)\\s-*\\(.*\\)" "-" 0 1 2 nil intern] 9 (#$ . 98686)])#@25 Keymap for VHDL models. (defvar vhdl-model-map nil (#$ . 99130))#@30 Initialize `vhdl-model-map'. (defalias 'vhdl-model-map-init #[0 "\302  \303\205 �@\262\304\3058\306\307@\"#\210A\262\202�\207" [vhdl-model-map vhdl-model-alist make-sparse-keymap nil define-key 2 vhdl-function-name "vhdl-model"] 8 (#$ . 99200)]) (vhdl-model-map-init)#@23 Keymap for VHDL Mode. (defvar vhdl-mode-map nil (#$ . 99483))#@29 Initialize `vhdl-mode-map'. (defalias 'vhdl-mode-map-init #[0 "\304 \305\306 #\210\305\307\n#\210\305\310\311#\210\305\312\313#\210\305\314\315#\210\305\316\317#\210\305\320\321#\210\305\322\323#\210\305\324\325#\210\305\326\327#\210\305\330\331#\210\305\332\333#\210\305\334\335#\210\305\336\337#\210\305\340\341#\210\305\342\343#\210\305\344\345#\210\305\346\347#\210\305\350\351#\210\305\352\353#\210\305\354\355#\210\305\356\357#\210\305\360\361#\210\305\362\361#\210\305\363\364#\210\305\365\366#\210\305\367\370#\210\305\371\372#\210\305\373\374#\210\305\375\376#\210\305\377\201@�#\210\305\201A�\201B�#\210\305\201C�\201D�#\210\305\201E�\201F�#\210\305\201G�\201H�#\210\305\201I�\201H�#\210\305\201J�\201K�#\210\305\201L�\201M�#\210\305\201N�\201O�#\210\305\201P�\201Q�#\210\305\201R�\201S�#\210\305\201T�\201U�#\210\305\201V�\201W�#\210\305\201X�\201Y�#\210\305\201Z�\201[�#\210\305\201\\�\201]�#\210\305\201^�\201_�#\210\305\201`�\201a�#\210\305\201b�\201c�#\210\305\201d�\201e�#\210\305\201f�\201g�#\210\305\201h�\201i�#\210\305\201j�\201k�#\210\305\201l�\201k�#\210\305\201m�\201n�#\210\305\201o�\201p�#\210\305\201q�\201r�#\210\305\201s�\201t�#\210\305\201u�\201v�#\210\305\201w�\201x�#\210\305\201y�\201z�#\210\305\201{�\201|�#\210\305\201}�\201|�#\210\305\201~�\201�#\210\305\201\200�\201\201�#\210\305\201\202�\201\203�#\210\305\201\204�\201\205�#\210\305\201\206�\201\207�#\210\305\201\210�\201\211�#\210\305\201\212�\201\213�#\210\305\201\214�\201\215�#\210\305\201\216�\201\217�#\210\305\201\220�\201\221�#\210\305\201\222�\201\223�#\210\305\201\224�\201\225�#\210\305\201\226�\201\227�#\210\305\201\230�\201\231�#\210\305\201\232�\201\233�#\210\305\201\234�\201\235�#\210\305\201\236�\201\237�#\210\305\201\240�\201\241�#\210\305\201\242�\201\243�#\210\305\201\244�\201\245�#\210\305\201\246�\201\247�#\210\305\201\250�\201\251�#\210\305\201\252�\201\253�#\210\305\201\254�\201\255�#\210\305\201\256�\201\257�#\210\305\201\260�\201\261�#\210\305\201\262�\201\263�#\210\305\201\264�\201\265�#\210\305\201\266�\201\267�#\210\305\201\270�\201\271�#\210\305\201\272�\201\273�#\210\305\201\274�\201\275�#\210\305\201\276�\201\277�#\210\305\201\300�\201\301�#\210 \203a\305\201\302�\201\303�#\210\305\201\304�\201\305�#\210\305\201\306�\201\307�#\210\305\201\310�\201\311�#\210\305\201\312�\201\313�#\210\305\201\314�\201\315�#\210\305\201\316�\201\317�#\210\305\201\320�\201\321�#\210\305\201\322�\201\323�#\210\201\324�\201\325�!\205\304\305\201\326�\201\327�#\207" [vhdl-mode-map vhdl-template-map vhdl-model-map vhdl-intelligent-tab make-sparse-keymap define-key "" " " "\341" vhdl-beginning-of-statement "\345" vhdl-end-of-statement "\206" vhdl-forward-sexp "\202" vhdl-backward-sexp "\225" vhdl-backward-up-list "\201" vhdl-backward-same-indent "\205" vhdl-forward-same-indent "\210" vhdl-mark-defun "\221" vhdl-indent-sexp "\336" vhdl-delete-indentation " " vhdl-electric-mode " " vhdl-stutter-mode "" vhdl-set-project "" vhdl-duplicate-project " " vhdl-import-project "" vhdl-export-project " " vhdl-set-compiler " " vhdl-compile "\213" vhdl-make "\353" vhdl-generate-makefile "" vhdl-port-copy "\367" "" vhdl-port-paste-entity "" vhdl-port-paste-component " " vhdl-port-paste-instance "" vhdl-port-paste-signals "\343" vhdl-port-paste-constants "" vhdl-port-paste-generic-map "" vhdl-port-paste-initializations "" vhdl-port-paste-testbench "" vhdl-port-flatten "" vhdl-port-reverse-direction "" vhdl-subprog-copy "\367" "" vhdl-subprog-paste-declaration "" vhdl-subprog-paste-body "" vhdl-subprog-paste-call "" vhdl-subprog-flatten " " vhdl-compose-new-component " " vhdl-compose-place-component " " vhdl-compose-wire-components " " vhdl-compose-configuration " " vhdl-compose-components-package "" vhdl-comment-uncomment-region "-" vhdl-comment-append-inline "\255" vhdl-comment-display-line " \f" indent-according-to-mode " " vhdl-indent-group "\234" indent-region " " vhdl-indent-buffer "" vhdl-align-group "" " " vhdl-align-same-indent "\f" vhdl-align-list "" vhdl-align-declarations "\341" vhdl-align-region "" vhdl-align-buffer "" vhdl-align-inline-comment-group "\343" vhdl-align-inline-comment-region "\f" vhdl-fill-list "" "" vhdl-fill-group " " vhdl-fill-same-indent "\346" vhdl-fill-region "\f" vhdl-line-kill "\f\367" vhdl-line-copy "\f" vhdl-line-yank "\f " vhdl-line-expand "\f" vhdl-line-transpose-next "\f" vhdl-line-transpose-previous "\f" vhdl-line-open "\f" goto-line "\f" vhdl-comment-uncomment-line "" vhdl-fix-statement-region "\363" vhdl-fix-statement-buffer "" vhdl-fix-clause "\343" vhdl-fix-case-region "" vhdl-fix-case-buffer "\367" vhdl-fixup-whitespace-region "" vhdl-fixup-whitespace-buffer "\342" vhdl-beautify-region "" vhdl-beautify-buffer "" vhdl-update-sensitivity-list-process "\363" vhdl-update-sensitivity-list-buffer " " vhdl-fontify-buffer " " vhdl-statistics-buffer "\355" vhdl-show-messages "" vhdl-doc-mode "" vhdl-version "\211" insert-tab " " vhdl-template-insert-construct " " vhdl-template-insert-package " " vhdl-template-insert-directive " " vhdl-model-insert " " vhdl-electric-space " " vhdl-electric-tab " " vhdl-electric-return "-" vhdl-electric-dash "[" vhdl-electric-open-bracket "]" vhdl-electric-close-bracket "'" vhdl-electric-quote ";" vhdl-electric-semicolon "," vhdl-electric-comma "." vhdl-electric-period vhdl-standard-p ams "=" vhdl-electric-equal] 4 (#$ . 99550)]) (vhdl-mode-map-init)#@42 Keymap for minibuffer used in VHDL Mode. (defvar vhdl-minibuffer-local-map (byte-code "\302 \303\"\210 \203�\304\305\306#\210\207" [minibuffer-local-map vhdl-word-completion-in-minibuffer make-sparse-keymap set-keymap-parent define-key " " vhdl-minibuffer-tab] 5) (#$ . 105224)) (mapc #[257 "\300\301\302#\210\300\303\302#\207" [put delete-selection t pending-delete] 5 "\n\n(fn SYM)"] '(vhdl-electric-space vhdl-electric-tab vhdl-electric-return vhdl-electric-dash vhdl-electric-open-bracket vhdl-electric-close-bracket vhdl-electric-quote vhdl-electric-semicolon vhdl-electric-comma vhdl-electric-period vhdl-electric-equal))#@43 Syntax table used in `vhdl-mode' buffers. (defvar vhdl-mode-syntax-table (byte-code "\301 \302\303\304#\210\302\305\304#\210\302\306\304#\210\302\307\304#\210\302\310\304#\210\302\311\304#\210\302\312\304#\210\302\313\304#\210\302\314\304#\210\302\315\304#\210\302\316\304#\210\302\317\304#\210\302\320\304#\210\302\321\304#\210\302\322\304#\210\302\323\324#\210\302\325\203l�\326\202m�\327#\210\302\330\331#\210\302\332\333#\210\302\311\334#\210\302\335\336#\210\302\337\336#\210\302\340\341#\210\302\342\343#\210\302\344\345#\210\302\346\347#\210\302\350\351#\210\302\352\353#\210\207" [vhdl-underscore-is-part-of-word make-syntax-table modify-syntax-entry 35 "." 36 37 38 39 42 43 46 58 59 60 61 62 92 124 34 "\"" 95 "w" "_" 45 ". 12b" 47 ". 14b" ". 23" 10 "> b" 13 40 "()" 41 ")(" 91 "(]" 93 ")[" 123 "(}" 125 "){"] 5) (#$ . 105863))#@59 Syntax table extended by `_' used in `vhdl-mode' buffers. (defvar vhdl-mode-ext-syntax-table (byte-code "\301!\302\303\304#\210\207" [vhdl-mode-syntax-table copy-syntax-table modify-syntax-entry 95 "w"] 5) (#$ . 106735))#@59 Buffer local variable containing syntactic analysis list. (defvar vhdl-syntactic-context nil (#$ . 106963)) (make-variable-buffer-local 'vhdl-syntactic-context)#@45 Abbrev table to use in `vhdl-mode' buffers. (defvar vhdl-mode-abbrev-table nil (#$ . 107129))#@38 Initialize `vhdl-mode-abbrev-table'. (defalias 'vhdl-mode-abbrev-table-init #[0 "\302\303\304\305>\205 �\306\307\310\"\305>\205�\311\312!\205�\306\313\314\"\315>\205R�\316\211 \211\203N�\211@\3178\262\320\232\204G�\320\321\322@\323#\324\325\257B\262A\266\202\202&�\210\266\202#\"\207" [vhdl-electric-keywords vhdl-model-alist define-abbrev-table vhdl-mode-abbrev-table append vhdl mapcar #[257 "\211@\300A\301\302\257\207" [#1="" 0 system] 6 "\n\n(fn X)"] (("--" . vhdl-template-display-comment-hook) ("abs" . vhdl-template-default-hook) ("access" . vhdl-template-default-hook) ("after" . vhdl-template-default-hook) ("alias" . vhdl-template-alias-hook) ("all" . vhdl-template-default-hook) ("and" . vhdl-template-default-hook) ("arch" . vhdl-template-architecture-hook) ("architecture" . vhdl-template-architecture-hook) ("array" . vhdl-template-default-hook) ("assert" . vhdl-template-assert-hook) ("attr" . vhdl-template-attribute-hook) ("attribute" . vhdl-template-attribute-hook) ("begin" . vhdl-template-default-indent-hook) ("block" . vhdl-template-block-hook) ("body" . vhdl-template-default-hook) ("buffer" . vhdl-template-default-hook) ("bus" . vhdl-template-default-hook) ("case" . vhdl-template-case-hook) ("comp" . vhdl-template-component-hook) ("component" . vhdl-template-component-hook) ("cond" . vhdl-template-conditional-signal-asst-hook) ("conditional" . vhdl-template-conditional-signal-asst-hook) ("conf" . vhdl-template-configuration-hook) ("configuration" . vhdl-template-configuration-hook) ("cons" . vhdl-template-constant-hook) ("constant" . vhdl-template-constant-hook) ("context" . vhdl-template-context-hook) ("disconnect" . vhdl-template-disconnect-hook) ("downto" . vhdl-template-default-hook) ("else" . vhdl-template-else-hook) ("elseif" . vhdl-template-elsif-hook) ("elsif" . vhdl-template-elsif-hook) ("end" . vhdl-template-default-indent-hook) ("entity" . vhdl-template-entity-hook) ("exit" . vhdl-template-exit-hook) ("file" . vhdl-template-file-hook) ("for" . vhdl-template-for-hook) ("func" . vhdl-template-function-hook) ("function" . vhdl-template-function-hook) ("generic" . vhdl-template-generic-hook) ("group" . vhdl-template-group-hook) ("guarded" . vhdl-template-default-hook) ("if" . vhdl-template-if-hook) ("impure" . vhdl-template-default-hook) ("in" . vhdl-template-default-hook) ("inertial" . vhdl-template-default-hook) ("inout" . vhdl-template-default-hook) ("inst" . vhdl-template-instance-hook) ("instance" . vhdl-template-instance-hook) ("is" . vhdl-template-default-hook) ("label" . vhdl-template-default-hook) ("library" . vhdl-template-library-hook) ("linkage" . vhdl-template-default-hook) ("literal" . vhdl-template-default-hook) ("loop" . vhdl-template-bare-loop-hook) ("map" . vhdl-template-map-hook) ("mod" . vhdl-template-default-hook) ("nand" . vhdl-template-default-hook) ("new" . vhdl-template-default-hook) ("next" . vhdl-template-next-hook) ("nor" . vhdl-template-default-hook) ("not" . vhdl-template-default-hook) ("null" . vhdl-template-default-hook) ("of" . vhdl-template-default-hook) ("on" . vhdl-template-default-hook) ("open" . vhdl-template-default-hook) ("or" . vhdl-template-default-hook) ("others" . vhdl-template-others-hook) ("out" . vhdl-template-default-hook) ("pack" . vhdl-template-package-hook) ("package" . vhdl-template-package-hook) ("port" . vhdl-template-port-hook) ("postponed" . vhdl-template-default-hook) ("procedure" . vhdl-template-procedure-hook) ("process" . vhdl-template-process-hook) ("pure" . vhdl-template-default-hook) ("range" . vhdl-template-default-hook) ("record" . vhdl-template-default-hook) ("register" . vhdl-template-default-hook) ("reject" . vhdl-template-default-hook) ("rem" . vhdl-template-default-hook) ("report" . vhdl-template-report-hook) ("return" . vhdl-template-return-hook) ("rol" . vhdl-template-default-hook) ("ror" . vhdl-template-default-hook) ("select" . vhdl-template-selected-signal-asst-hook) ("severity" . vhdl-template-default-hook) ("shared" . vhdl-template-default-hook) ("sig" . vhdl-template-signal-hook) ("signal" . vhdl-template-signal-hook) ("sla" . vhdl-template-default-hook) ("sll" . vhdl-template-default-hook) ("sra" . vhdl-template-default-hook) ("srl" . vhdl-template-default-hook) ("subtype" . vhdl-template-subtype-hook) ("then" . vhdl-template-default-hook) ("to" . vhdl-template-default-hook) ("transport" . vhdl-template-default-hook) ("type" . vhdl-template-type-hook) ("unaffected" . vhdl-template-default-hook) ("units" . vhdl-template-default-hook) ("until" . vhdl-template-default-hook) ("use" . vhdl-template-use-hook) ("var" . vhdl-template-variable-hook) ("variable" . vhdl-template-variable-hook) ("wait" . vhdl-template-wait-hook) ("when" . vhdl-template-when-hook) ("while" . vhdl-template-while-loop-hook) ("with" . vhdl-template-with-hook) ("xnor" . vhdl-template-default-hook) ("xor" . vhdl-template-default-hook)) vhdl-standard-p ams #[257 "\211@\300A\301\302\257\207" [#1# 0 system] 6 "\n\n(fn X)"] (("across" . vhdl-template-default-hook) ("break" . vhdl-template-break-hook) ("limit" . vhdl-template-limit-hook) ("nature" . vhdl-template-nature-hook) ("noise" . vhdl-template-default-hook) ("procedural" . vhdl-template-procedural-hook) ("quantity" . vhdl-template-quantity-hook) ("reference" . vhdl-template-default-hook) ("spectrum" . vhdl-template-default-hook) ("subnature" . vhdl-template-subnature-hook) ("terminal" . vhdl-template-terminal-hook) ("through" . vhdl-template-default-hook) ("tolerance" . vhdl-template-default-hook)) user nil 3 #1# vhdl-function-name "vhdl-model" "hook" 0 system] 15 (#$ . 107228)]) (vhdl-mode-abbrev-table-init)#@39 List of built-in construct templates. (defvar vhdl-template-construct-alist nil (#$ . 112877))#@45 Initialize `vhdl-template-construct-alist'. (defalias 'vhdl-template-construct-alist-init #[0 "\301\302\303\304!\205 �\305\"\211\207" [vhdl-template-construct-alist append (("alias declaration" vhdl-template-alias) ("architecture body" vhdl-template-architecture) ("assertion" vhdl-template-assert) ("attribute declaration" vhdl-template-attribute-decl) ("attribute specification" vhdl-template-attribute-spec) ("block configuration" vhdl-template-block-configuration) ("block statement" vhdl-template-block) ("case statement" vhdl-template-case-is) ("component configuration" vhdl-template-component-conf) ("component declaration" vhdl-template-component-decl) ("component instantiation statement" vhdl-template-component-inst) ("conditional signal assignment" vhdl-template-conditional-signal-asst) ("configuration declaration" vhdl-template-configuration-decl) ("configuration specification" vhdl-template-configuration-spec) ("constant declaration" vhdl-template-constant) ("context declaration" vhdl-template-context) ("disconnection specification" vhdl-template-disconnect) ("entity declaration" vhdl-template-entity) ("exit statement" vhdl-template-exit) ("file declaration" vhdl-template-file) ("generate statement" vhdl-template-generate) ("generic clause" vhdl-template-generic) ("group declaration" vhdl-template-group-decl) ("group template declaration" vhdl-template-group-template) ("if statement" vhdl-template-if-then) ("library clause" vhdl-template-library) ("loop statement" vhdl-template-loop) ("next statement" vhdl-template-next) ("package declaration" vhdl-template-package-decl) ("package body" vhdl-template-package-body) ("port clause" vhdl-template-port) ("process statement" vhdl-template-process) ("report statement" vhdl-template-report) ("return statement" vhdl-template-return) ("selected signal assignment" vhdl-template-selected-signal-asst) ("signal declaration" vhdl-template-signal) ("subprogram declaration" vhdl-template-subprogram-decl) ("subprogram body" vhdl-template-subprogram-body) ("subtype declaration" vhdl-template-subtype) ("type declaration" vhdl-template-type) ("use clause" vhdl-template-use) ("variable declaration" vhdl-template-variable) ("wait statement" vhdl-template-wait)) vhdl-standard-p ams (("break statement" vhdl-template-break) ("nature declaration" vhdl-template-nature) ("quantity declaration" vhdl-template-quantity) ("simultaneous case statement" vhdl-template-case-use) ("simultaneous if statement" vhdl-template-if-use) ("simultaneous procedural statement" vhdl-template-procedural) ("step limit specification" vhdl-template-limit) ("subnature declaration" vhdl-template-subnature) ("terminal declaration" vhdl-template-terminal))] 4 (#$ . 112977)]) (vhdl-template-construct-alist-init)#@37 List of built-in package templates. (defvar vhdl-template-package-alist nil (#$ . 115742))#@43 Initialize `vhdl-template-package-alist'. (defalias 'vhdl-template-package-alist-init #[0 "\301\302\303\304!\205 �\305\"\211\207" [vhdl-template-package-alist append (("numeric_bit" vhdl-template-package-numeric-bit) ("numeric_std" vhdl-template-package-numeric-std) ("std_logic_1164" vhdl-template-package-std-logic-1164) ("std_logic_arith" vhdl-template-package-std-logic-arith) ("std_logic_misc" vhdl-template-package-std-logic-misc) ("std_logic_signed" vhdl-template-package-std-logic-signed) ("std_logic_textio" vhdl-template-package-std-logic-textio) ("std_logic_unsigned" vhdl-template-package-std-logic-unsigned) ("textio" vhdl-template-package-textio)) vhdl-standard-p math (("math_complex" vhdl-template-package-math-complex) ("math_real" vhdl-template-package-math-real))] 4 (#$ . 115838)]) (vhdl-template-package-alist-init)#@39 List of built-in directive templates. (defvar vhdl-template-directive-alist '(("translate_on" vhdl-template-directive-translate-on) ("translate_off" vhdl-template-directive-translate-off) ("synthesis_on" vhdl-template-directive-synthesis-on) ("synthesis_off" vhdl-template-directive-synthesis-off)) (#$ . 116681))#@54 Call the customize function with `vhdl' as argument. (defalias 'vhdl-customize #[0 "\300\301!\207" [customize-browse vhdl] 2 (#$ . 117000) nil])#@24 Create VHDL Mode menu. (defalias 'vhdl-create-mode-menu #[0 "\304\305\306\307\211\203*�@@\262\310\311D\312\313\314\315\316BB&B\262A\262\202� \2035�\317\320\"\2027�\237\262\321\322\"\266\203\323#\324\325\326\327\324\330\331\324\332\333\334\324\305\335\n\307\211\203w�@@\262\310\336\337E\312\313\314\315\340BB&B\262A\262\202R�\237\262\321\341\"\266\203\342#\257\f\324\305\343\344\345!\205\217�\346\347\305\350\344\345!\205\231�\351\344\352!\205\240�\353\354$C\355%\305\356 \307\211\203\317�@\262\310@\357\360@\"\361\362\363\3648!P$B\262A\262\202\252�\237\262\321\365\"\266\203\366#\367\370\371\324\372\373\374\324\375\376\377\201@�\201A�\201B�\324\201C�\201D�\201E�\201F�\324\201G�\201H�\324\201I�\201J�\201K�\324\201L�\201M�\322\201N�\305\201O�\307\211\203Q@@\262\310\201P�\201Q�\201R�E\311DE\312\313\314\315\201S�BB&B\262A\262\202\237\262\321\322\"\266\203\"\201T�BBB\341\201U�\201V�\n\307\211\203\227@@\262\310\201Q�\201W�E\312\313\314\315\201X�BB&B\262A\262\202l\237\262\321\341\"\266\203B\201Y�BBB\201Z�BBBB\257#\207" [vhdl-project-alist vhdl-project-sort vhdl-compiler-alist vhdl-model-alist "VHDL" append ("Project" ["None" (vhdl-set-project #1="") :style radio :selected (null vhdl-project)] "--") nil vector vhdl-set-project :style radio :selected equal (vhdl-project) sort #[514 "\300\234\300\234\231\207" [0] 5 "\n\n(fn A B)"] vhdl-menu-split "Project" ("--" "--" ["Select Project..." vhdl-set-project t] ["Set As Default Project" vhdl-set-default-project t] "--" ["Duplicate Project" vhdl-duplicate-project vhdl-project] ["Import Project..." vhdl-import-project :keys "C-c C-p C-m" :active t] ["Export Project" vhdl-export-project vhdl-project] "--" ["Customize Project..." (customize-option 'vhdl-project-alist) t]) "--" "Compile" ["Compile Buffer" vhdl-compile t] ["Stop Compilation" kill-compilation t] ["Make" vhdl-make t] ["Generate Makefile" vhdl-generate-makefile t] ["Next Error" next-error t] ["Previous Error" previous-error t] ["First Error" first-error t] ("Compiler") setq vhdl-compiler (vhdl-compiler) "Compiler" ("--" "--" ["Select Compiler..." vhdl-set-compiler t] "--" ["Customize Compiler..." (customize-option 'vhdl-compiler-alist) t]) ("Template" ("VHDL Construct 1" ["Alias" vhdl-template-alias t] ["Architecture" vhdl-template-architecture t] ["Assert" vhdl-template-assert t] ["Attribute (Decl)" vhdl-template-attribute-decl t] ["Attribute (Spec)" vhdl-template-attribute-spec t] ["Block" vhdl-template-block t] ["Case" vhdl-template-case-is t] ["Component (Decl)" vhdl-template-component-decl t] ["(Component) Instance" vhdl-template-component-inst t] ["Conditional (Signal Asst)" vhdl-template-conditional-signal-asst t] ["Configuration (Block)" vhdl-template-block-configuration t] ["Configuration (Comp)" vhdl-template-component-conf t] ["Configuration (Decl)" vhdl-template-configuration-decl t] ["Configuration (Spec)" vhdl-template-configuration-spec t] ["Constant" vhdl-template-constant t] ["Context" vhdl-template-context t] ["Disconnect" vhdl-template-disconnect t] ["Else" vhdl-template-else t] ["Elsif" vhdl-template-elsif t] ["Entity" vhdl-template-entity t] ["Exit" vhdl-template-exit t] ["File" vhdl-template-file t] ["For (Generate)" vhdl-template-for-generate t] ["For (Loop)" vhdl-template-for-loop t] ["Function (Body)" vhdl-template-function-body t] ["Function (Decl)" vhdl-template-function-decl t] ["Generic" vhdl-template-generic t] ["Group (Decl)" vhdl-template-group-decl t] ["Group (Template)" vhdl-template-group-template t]) ("VHDL Construct 2" ["If (Generate)" vhdl-template-if-generate t] ["If (Then)" vhdl-template-if-then t] ["Library" vhdl-template-library t] ["Loop" vhdl-template-bare-loop t] ["Map" vhdl-template-map t] ["Next" vhdl-template-next t] ["Others (Aggregate)" vhdl-template-others t] ["Package (Decl)" vhdl-template-package-decl t] ["Package (Body)" vhdl-template-package-body t] ["Port" vhdl-template-port t] ["Procedure (Body)" vhdl-template-procedure-body t] ["Procedure (Decl)" vhdl-template-procedure-decl t] ["Process (Comb)" vhdl-template-process-comb t] ["Process (Seq)" vhdl-template-process-seq t] ["Report" vhdl-template-report t] ["Return" vhdl-template-return t] ["Select" vhdl-template-selected-signal-asst t] ["Signal" vhdl-template-signal t] ["Subtype" vhdl-template-subtype t] ["Type" vhdl-template-type t] ["Use" vhdl-template-use t] ["Variable" vhdl-template-variable t] ["Wait" vhdl-template-wait t] ["(Clocked Wait)" vhdl-template-clocked-wait t] ["When" vhdl-template-when t] ["While (Loop)" vhdl-template-while-loop t] ["With" vhdl-template-with t])) vhdl-standard-p ams (("VHDL-AMS Construct" ["Break" vhdl-template-break t] ["Case (Use)" vhdl-template-case-use t] ["If (Use)" vhdl-template-if-use t] ["Limit" vhdl-template-limit t] ["Nature" vhdl-template-nature t] ["Procedural" vhdl-template-procedural t] ["Quantity (Free)" vhdl-template-quantity-free t] ["Quantity (Branch)" vhdl-template-quantity-branch t] ["Quantity (Source)" vhdl-template-quantity-source t] ["Subnature" vhdl-template-subnature t] ["Terminal" vhdl-template-terminal t])) (["Insert Construct..." vhdl-template-insert-construct :keys "C-c C-i C-t"] "--") ("Package" ["numeric_bit" vhdl-template-package-numeric-bit t] ["numeric_std" vhdl-template-package-numeric-std t] ["std_logic_1164" vhdl-template-package-std-logic-1164 t] ["textio" vhdl-template-package-textio t] "--" ["std_logic_arith" vhdl-template-package-std-logic-arith t] ["std_logic_signed" vhdl-template-package-std-logic-signed t] ["std_logic_unsigned" vhdl-template-package-std-logic-unsigned t] ["std_logic_misc" vhdl-template-package-std-logic-misc t] ["std_logic_textio" vhdl-template-package-std-logic-textio t] "--") (["fundamental_constants" vhdl-template-package-fundamental-constants t] ["material_constants" vhdl-template-package-material-constants t] ["energy_systems" vhdl-template-package-energy-systems t] ["electrical_systems" vhdl-template-package-electrical-systems t] ["mechanical_systems" vhdl-template-package-mechanical-systems t] ["radiant_systems" vhdl-template-package-radiant-systems t] ["thermal_systems" vhdl-template-package-thermal-systems t] ["fluidic_systems" vhdl-template-package-fluidic-systems t] "--") math (["math_complex" vhdl-template-package-math-complex t] ["math_real" vhdl-template-package-math-real t] "--") (["Insert Package..." vhdl-template-insert-package :keys "C-c C-i C-p"]) (("Directive" ["translate_on" vhdl-template-directive-translate-on t] ["translate_off" vhdl-template-directive-translate-off t] ["synthesis_on" vhdl-template-directive-synthesis-on t] ["synthesis_off" vhdl-template-directive-synthesis-off t] "--" ["Insert Directive..." vhdl-template-insert-directive :keys "C-c C-i C-d"]) "--" ["Insert Header" vhdl-template-header :keys "C-c C-t C-h"] ["Insert Footer" vhdl-template-footer t] ["Insert Date" vhdl-template-insert-date t] ["Modify Date" vhdl-template-modify :keys "C-c C-t C-m"] "--" ["Query Next Prompt" vhdl-template-search-prompt t]) ("Model") vhdl-function-name "vhdl-model" :keys "C-c C-m " key-description 2 "Model" ("--" "--" ["Insert Model..." vhdl-model-insert :keys "C-c C-i C-m"] ["Customize Model..." (customize-option 'vhdl-model-alist) t]) ("Port" ["Copy" vhdl-port-copy t] "--" ["Paste As Entity" vhdl-port-paste-entity vhdl-port-list] ["Paste As Component" vhdl-port-paste-component vhdl-port-list] ["Paste As Instance" vhdl-port-paste-instance :keys "C-c C-p C-i" :active vhdl-port-list] ["Paste As Signals" vhdl-port-paste-signals vhdl-port-list] ["Paste As Constants" vhdl-port-paste-constants vhdl-port-list] ["Paste As Generic Map" vhdl-port-paste-generic-map vhdl-port-list] ["Paste As Initializations" vhdl-port-paste-initializations vhdl-port-list] "--" ["Paste As Testbench" vhdl-port-paste-testbench vhdl-port-list] "--" ["Flatten" vhdl-port-flatten :style toggle :selected vhdl-port-flattened :active vhdl-port-list] ["Reverse Direction" vhdl-port-reverse-direction :style toggle :selected vhdl-port-reversed-direction :active vhdl-port-list]) ("Compose" ["New Component" vhdl-compose-new-component t] ["Copy Component" vhdl-port-copy t] ["Place Component" vhdl-compose-place-component vhdl-port-list] ["Wire Components" vhdl-compose-wire-components t] "--" ["Generate Configuration" vhdl-compose-configuration t] ["Generate Components Package" vhdl-compose-components-package t]) ("Subprogram" ["Copy" vhdl-subprog-copy t] "--" ["Paste As Declaration" vhdl-subprog-paste-declaration vhdl-subprog-list] ["Paste As Body" vhdl-subprog-paste-body vhdl-subprog-list] ["Paste As Call" vhdl-subprog-paste-call vhdl-subprog-list] "--" ["Flatten" vhdl-subprog-flatten :style toggle :selected vhdl-subprog-flattened :active vhdl-subprog-list]) ("Comment" ["(Un)Comment Out Region" vhdl-comment-uncomment-region (mark)] "--" ["Insert Inline Comment" vhdl-comment-append-inline t] ["Insert Horizontal Line" vhdl-comment-display-line t] ["Insert Display Comment" vhdl-comment-display t] "--" ["Fill Comment" fill-paragraph t] ["Fill Comment Region" fill-region (mark)] ["Kill Comment Region" vhdl-comment-kill-region (mark)] ["Kill Inline Comment Region" vhdl-comment-kill-inline-region (mark)]) ("Line" ["Kill" vhdl-line-kill t] ["Copy" vhdl-line-copy t] ["Yank" vhdl-line-yank t] ["Expand" vhdl-line-expand t] "--" ["Transpose Next" vhdl-line-transpose-next t] ["Transpose Prev" vhdl-line-transpose-previous t] ["Open" vhdl-line-open t] ["Join" vhdl-delete-indentation t] "--" ["Goto" goto-line t] ["(Un)Comment Out" vhdl-comment-uncomment-line t]) ("Move" ["Forward Statement" vhdl-end-of-statement t] ["Backward Statement" vhdl-beginning-of-statement t] ["Forward Expression" vhdl-forward-sexp t] ["Backward Expression" vhdl-backward-sexp t] ["Forward Same Indent" vhdl-forward-same-indent t] ["Backward Same Indent" vhdl-backward-same-indent t] ["Forward Function" vhdl-end-of-defun t] ["Backward Function" vhdl-beginning-of-defun t] ["Mark Function" vhdl-mark-defun t]) ("Indent" ["Line" indent-according-to-mode :keys "C-c C-i C-l"] ["Group" vhdl-indent-group :keys "C-c C-i C-g"] ["Region" indent-region (mark)] ["Buffer" vhdl-indent-buffer :keys "C-c C-i C-b"]) ("Align" ["Group" vhdl-align-group t] ["Same Indent" vhdl-align-same-indent :keys "C-c C-a C-i"] ["List" vhdl-align-list t] ["Declarations" vhdl-align-declarations t] ["Region" vhdl-align-region (mark)] ["Buffer" vhdl-align-buffer t] "--" ["Inline Comment Group" vhdl-align-inline-comment-group t] ["Inline Comment Region" vhdl-align-inline-comment-region (mark)] ["Inline Comment Buffer" vhdl-align-inline-comment-buffer t]) ("Fill" ["List" vhdl-fill-list t] ["Group" vhdl-fill-group t] ["Same Indent" vhdl-fill-same-indent :keys "C-c C-f C-i"] ["Region" vhdl-fill-region (mark)]) ("Beautify" ["Region" vhdl-beautify-region (mark)] ["Buffer" vhdl-beautify-buffer t]) ("Fix" ["Generic/Port Clause" vhdl-fix-clause t] ["Generic/Port Clause Buffer" vhdl-fix-clause t] "--" ["Case Region" vhdl-fix-case-region (mark)] ["Case Buffer" vhdl-fix-case-buffer t] "--" ["Whitespace Region" vhdl-fixup-whitespace-region (mark)] ["Whitespace Buffer" vhdl-fixup-whitespace-buffer t] "--" ["Statement Region" vhdl-fix-statement-region (mark)] ["Statement Buffer" vhdl-fix-statement-buffer t] "--" ["Trailing Spaces Buffer" vhdl-remove-trailing-spaces t]) ("Update" ["Sensitivity List" vhdl-update-sensitivity-list-process t] ["Sensitivity List Buffer" vhdl-update-sensitivity-list-buffer t]) ["Fontify Buffer" vhdl-fontify-buffer t] ["Statistics Buffer" vhdl-statistics-buffer t] ["Show Messages" vhdl-show-messages t] ["Syntactic Info" vhdl-show-syntactic-information t] ["Speedbar" vhdl-speedbar t] ["Hide/Show" vhdl-hs-minor-mode t] ("Documentation" ["VHDL Mode" vhdl-doc-mode :keys "C-c C-h"] ["Release Notes" (vhdl-doc-variable 'vhdl-doc-release-notes) t] ["Reserved Words" (vhdl-doc-variable 'vhdl-doc-keywords) t] ["Coding Style" (vhdl-doc-variable 'vhdl-doc-coding-style) t]) ["Version" vhdl-version t] ["Bug Report..." vhdl-submit-bug-report t] "Options" ("Mode" ["Electric Mode" (progn (customize-set-variable 'vhdl-electric-mode (not vhdl-electric-mode)) (vhdl-mode-line-update)) :style toggle :selected vhdl-electric-mode :keys "C-c C-m C-e"] ["Stutter Mode" (progn (customize-set-variable 'vhdl-stutter-mode (not vhdl-stutter-mode)) (vhdl-mode-line-update)) :style toggle :selected vhdl-stutter-mode :keys "C-c C-m C-s"] ["Indent Tabs Mode" (progn (customize-set-variable 'vhdl-indent-tabs-mode (not vhdl-indent-tabs-mode)) (setq indent-tabs-mode vhdl-indent-tabs-mode)) :style toggle :selected vhdl-indent-tabs-mode] "--" ["Customize Group..." (customize-group 'vhdl-mode) t]) ["Project Setup..." (customize-option 'vhdl-project-alist) t] ("Selected Project at Startup" ["None" (progn (customize-set-variable 'vhdl-project nil) (vhdl-set-project #1#)) :style radio :selected (null vhdl-project)] "--") progn customize-set-variable 'vhdl-project (vhdl-project) (["Setup File Name..." (customize-option 'vhdl-project-file-name) t] ("Auto Load Setup File" ["At Startup" (customize-set-variable 'vhdl-project-autoload (if (memq 'startup vhdl-project-autoload) (delq 'startup vhdl-project-autoload) (cons 'startup vhdl-project-autoload))) :style toggle :selected (memq 'startup vhdl-project-autoload)]) ["Sort Projects" (customize-set-variable 'vhdl-project-sort (not vhdl-project-sort)) :style toggle :selected vhdl-project-sort] "--" ["Customize Group..." (customize-group 'vhdl-project) t]) ["Compiler Setup..." (customize-option 'vhdl-compiler-alist) t] "Selected Compiler at Startup" 'vhdl-compiler (vhdl-compiler) (["Use Local Error Regexp" (customize-set-variable 'vhdl-compile-use-local-error-regexp (not vhdl-compile-use-local-error-regexp)) :style toggle :selected vhdl-compile-use-local-error-regexp] ["Makefile Default Targets..." (customize-option 'vhdl-makefile-default-targets) t] ["Makefile Generation Hook..." (customize-option 'vhdl-makefile-generation-hook) t] ["Default Library Name" (customize-option 'vhdl-default-library) t] "--" ["Customize Group..." (customize-group 'vhdl-compiler) t]) (("Style" ("VHDL Standard" ["VHDL'87" (progn (customize-set-variable 'vhdl-standard (list '87 (cadr vhdl-standard))) (vhdl-activate-customizations)) :style radio :selected (eq '87 (car vhdl-standard))] ["VHDL'93/02" (progn (customize-set-variable 'vhdl-standard (list '93 (cadr vhdl-standard))) (vhdl-activate-customizations)) :style radio :selected (eq '93 (car vhdl-standard))] ["VHDL'08" (progn (customize-set-variable 'vhdl-standard (list '8 (cadr vhdl-standard))) (vhdl-activate-customizations)) :style radio :selected (eq '8 (car vhdl-standard))] "--" ["VHDL-AMS" (progn (customize-set-variable 'vhdl-standard (list (car vhdl-standard) (if (memq 'ams (cadr vhdl-standard)) (delq 'ams (cadr vhdl-standard)) (cons 'ams (cadr vhdl-standard))))) (vhdl-activate-customizations)) :style toggle :selected (memq 'ams (cadr vhdl-standard))] ["Math Packages" (progn (customize-set-variable 'vhdl-standard (list (car vhdl-standard) (if (memq 'math (cadr vhdl-standard)) (delq 'math (cadr vhdl-standard)) (cons 'math (cadr vhdl-standard))))) (vhdl-activate-customizations)) :style toggle :selected (memq 'math (cadr vhdl-standard))]) ["Indentation Offset..." (customize-option 'vhdl-basic-offset) t] ["Upper Case Keywords" (customize-set-variable 'vhdl-upper-case-keywords (not vhdl-upper-case-keywords)) :style toggle :selected vhdl-upper-case-keywords] ["Upper Case Types" (customize-set-variable 'vhdl-upper-case-types (not vhdl-upper-case-types)) :style toggle :selected vhdl-upper-case-types] ["Upper Case Attributes" (customize-set-variable 'vhdl-upper-case-attributes (not vhdl-upper-case-attributes)) :style toggle :selected vhdl-upper-case-attributes] ["Upper Case Enumeration Values" (customize-set-variable 'vhdl-upper-case-enum-values (not vhdl-upper-case-enum-values)) :style toggle :selected vhdl-upper-case-enum-values] ["Upper Case Constants" (customize-set-variable 'vhdl-upper-case-constants (not vhdl-upper-case-constants)) :style toggle :selected vhdl-upper-case-constants] ("Use Direct Instantiation" ["Never" (customize-set-variable 'vhdl-use-direct-instantiation 'never) :style radio :selected (eq 'never vhdl-use-direct-instantiation)] ["Standard" (customize-set-variable 'vhdl-use-direct-instantiation 'standard) :style radio :selected (eq 'standard vhdl-use-direct-instantiation)] ["Always" (customize-set-variable 'vhdl-use-direct-instantiation 'always) :style radio :selected (eq 'always vhdl-use-direct-instantiation)]) ["Include Array Index and Record Field in Sensitivity List" (customize-set-variable 'vhdl-array-index-record-field-in-sensitivity-list (not vhdl-array-index-record-field-in-sensitivity-list)) :style toggle :selected vhdl-array-index-record-field-in-sensitivity-list] "--" ["Customize Group..." (customize-group 'vhdl-style) t]) ("Naming" ["Entity File Name..." (customize-option 'vhdl-entity-file-name) t] ["Architecture File Name..." (customize-option 'vhdl-architecture-file-name) t] ["Configuration File Name..." (customize-option 'vhdl-configuration-file-name) t] ["Package File Name..." (customize-option 'vhdl-package-file-name) t] ("File Name Case" ["As Is" (customize-set-variable 'vhdl-file-name-case 'identity) :style radio :selected (eq 'identity vhdl-file-name-case)] ["Lower Case" (customize-set-variable 'vhdl-file-name-case 'downcase) :style radio :selected (eq 'downcase vhdl-file-name-case)] ["Upper Case" (customize-set-variable 'vhdl-file-name-case 'upcase) :style radio :selected (eq 'upcase vhdl-file-name-case)] ["Capitalize" (customize-set-variable 'vhdl-file-name-case 'capitalize) :style radio :selected (eq 'capitalize vhdl-file-name-case)]) "--" ["Customize Group..." (customize-group 'vhdl-naming) t]) ("Template" ("Electric Keywords" ["VHDL Keywords" (customize-set-variable 'vhdl-electric-keywords (if (memq 'vhdl vhdl-electric-keywords) (delq 'vhdl vhdl-electric-keywords) (cons 'vhdl vhdl-electric-keywords))) :style toggle :selected (memq 'vhdl vhdl-electric-keywords)] ["User Model Keywords" (customize-set-variable 'vhdl-electric-keywords (if (memq 'user vhdl-electric-keywords) (delq 'user vhdl-electric-keywords) (cons 'user vhdl-electric-keywords))) :style toggle :selected (memq 'user vhdl-electric-keywords)]) ("Insert Optional Labels" ["None" (customize-set-variable 'vhdl-optional-labels 'none) :style radio :selected (eq 'none vhdl-optional-labels)] ["Processes Only" (customize-set-variable 'vhdl-optional-labels 'process) :style radio :selected (eq 'process vhdl-optional-labels)] ["All Constructs" (customize-set-variable 'vhdl-optional-labels 'all) :style radio :selected (eq 'all vhdl-optional-labels)]) ("Insert Empty Lines" ["None" (customize-set-variable 'vhdl-insert-empty-lines 'none) :style radio :selected (eq 'none vhdl-insert-empty-lines)] ["Design Units Only" (customize-set-variable 'vhdl-insert-empty-lines 'unit) :style radio :selected (eq 'unit vhdl-insert-empty-lines)] ["All Constructs" (customize-set-variable 'vhdl-insert-empty-lines 'all) :style radio :selected (eq 'all vhdl-insert-empty-lines)]) ["Argument List Indent" (customize-set-variable 'vhdl-argument-list-indent (not vhdl-argument-list-indent)) :style toggle :selected vhdl-argument-list-indent] ["Association List with Formals" (customize-set-variable 'vhdl-association-list-with-formals (not vhdl-association-list-with-formals)) :style toggle :selected vhdl-association-list-with-formals] ["Conditions in Parenthesis" (customize-set-variable 'vhdl-conditions-in-parenthesis (not vhdl-conditions-in-parenthesis)) :style toggle :selected vhdl-conditions-in-parenthesis] ["Sensitivity List uses 'all'" (customize-set-variable 'vhdl-sensitivity-list-all (not vhdl-sensitivity-list-all)) :style toggle :selected vhdl-sensitivity-list-all] ["Zero String..." (customize-option 'vhdl-zero-string) t] ["One String..." (customize-option 'vhdl-one-string) t] ("File Header" ["Header String..." (customize-option 'vhdl-file-header) t] ["Footer String..." (customize-option 'vhdl-file-footer) t] ["Company Name..." (customize-option 'vhdl-company-name) t] ["Copyright String..." (customize-option 'vhdl-copyright-string) t] ["Platform Specification..." (customize-option 'vhdl-platform-spec) t] ["Date Format..." (customize-option 'vhdl-date-format) t] ["Modify Date Prefix String..." (customize-option 'vhdl-modify-date-prefix-string) t] ["Modify Date on Saving" (progn (customize-set-variable 'vhdl-modify-date-on-saving (not vhdl-modify-date-on-saving)) (vhdl-activate-customizations)) :style toggle :selected vhdl-modify-date-on-saving]) ("Sequential Process" ("Kind of Reset" ["None" (customize-set-variable 'vhdl-reset-kind 'none) :style radio :selected (eq 'none vhdl-reset-kind)] ["Synchronous" (customize-set-variable 'vhdl-reset-kind 'sync) :style radio :selected (eq 'sync vhdl-reset-kind)] ["Asynchronous" (customize-set-variable 'vhdl-reset-kind 'async) :style radio :selected (eq 'async vhdl-reset-kind)] ["Query" (customize-set-variable 'vhdl-reset-kind 'query) :style radio :selected (eq 'query vhdl-reset-kind)]) ["Reset is Active High" (customize-set-variable 'vhdl-reset-active-high (not vhdl-reset-active-high)) :style toggle :selected vhdl-reset-active-high] ["Use Rising Clock Edge" (customize-set-variable 'vhdl-clock-rising-edge (not vhdl-clock-rising-edge)) :style toggle :selected vhdl-clock-rising-edge] ("Clock Edge Condition" ["Standard" (customize-set-variable 'vhdl-clock-edge-condition 'standard) :style radio :selected (eq 'standard vhdl-clock-edge-condition)] ["Function \"rising_edge\"" (customize-set-variable 'vhdl-clock-edge-condition 'function) :style radio :selected (eq 'function vhdl-clock-edge-condition)]) ["Clock Name..." (customize-option 'vhdl-clock-name) t] ["Reset Name..." (customize-option 'vhdl-reset-name) t]) "--" ["Customize Group..." (customize-group 'vhdl-template) t]) ("Model" ["Model Definition..." (customize-option 'vhdl-model-alist) t]) ("Port" ["Include Port Comments" (customize-set-variable 'vhdl-include-port-comments (not vhdl-include-port-comments)) :style toggle :selected vhdl-include-port-comments] ["Include Direction Comments" (customize-set-variable 'vhdl-include-direction-comments (not vhdl-include-direction-comments)) :style toggle :selected vhdl-include-direction-comments] ["Include Type Comments" (customize-set-variable 'vhdl-include-type-comments (not vhdl-include-type-comments)) :style toggle :selected vhdl-include-type-comments] ("Include Group Comments" ["Never" (customize-set-variable 'vhdl-include-group-comments 'never) :style radio :selected (eq 'never vhdl-include-group-comments)] ["Declarations" (customize-set-variable 'vhdl-include-group-comments 'decl) :style radio :selected (eq 'decl vhdl-include-group-comments)] ["Always" (customize-set-variable 'vhdl-include-group-comments 'always) :style radio :selected (eq 'always vhdl-include-group-comments)]) ["Actual Generic Name..." (customize-option 'vhdl-actual-generic-name) t] ["Actual Port Name..." (customize-option 'vhdl-actual-port-name) t] ["Instance Name..." (customize-option 'vhdl-instance-name) t] ("Testbench" ["Entity Name..." (customize-option 'vhdl-testbench-entity-name) t] ["Architecture Name..." (customize-option 'vhdl-testbench-architecture-name) t] ["Configuration Name..." (customize-option 'vhdl-testbench-configuration-name) t] ["DUT Name..." (customize-option 'vhdl-testbench-dut-name) t] ["Include Header" (customize-set-variable 'vhdl-testbench-include-header (not vhdl-testbench-include-header)) :style toggle :selected vhdl-testbench-include-header] ["Declarations..." (customize-option 'vhdl-testbench-declarations) t] ["Statements..." (customize-option 'vhdl-testbench-statements) t] ["Initialize Signals" (customize-set-variable 'vhdl-testbench-initialize-signals (not vhdl-testbench-initialize-signals)) :style toggle :selected vhdl-testbench-initialize-signals] ["Include Library Clause" (customize-set-variable 'vhdl-testbench-include-library (not vhdl-testbench-include-library)) :style toggle :selected vhdl-testbench-include-library] ["Include Configuration" (customize-set-variable 'vhdl-testbench-include-configuration (not vhdl-testbench-include-configuration)) :style toggle :selected vhdl-testbench-include-configuration] ("Create Files" ["None" (customize-set-variable 'vhdl-testbench-create-files 'none) :style radio :selected (eq 'none vhdl-testbench-create-files)] ["Single" (customize-set-variable 'vhdl-testbench-create-files 'single) :style radio :selected (eq 'single vhdl-testbench-create-files)] ["Separate" (customize-set-variable 'vhdl-testbench-create-files 'separate) :style radio :selected (eq 'separate vhdl-testbench-create-files)]) ["Testbench Entity File Name..." (customize-option 'vhdl-testbench-entity-file-name) t] ["Testbench Architecture File Name..." (customize-option 'vhdl-testbench-architecture-file-name) t]) "--" ["Customize Group..." (customize-group 'vhdl-port) t]) ("Compose" ["Architecture Name..." (customize-option 'vhdl-compose-architecture-name) t] ["Configuration Name..." (customize-option 'vhdl-compose-configuration-name) t] ["Components Package Name..." (customize-option 'vhdl-components-package-name) t] ["Use Components Package" (customize-set-variable 'vhdl-use-components-package (not vhdl-use-components-package)) :style toggle :selected vhdl-use-components-package] ["Include Header" (customize-set-variable 'vhdl-compose-include-header (not vhdl-compose-include-header)) :style toggle :selected vhdl-compose-include-header] ("Create Entity/Architecture Files" ["None" (customize-set-variable 'vhdl-compose-create-files 'none) :style radio :selected (eq 'none vhdl-compose-create-files)] ["Single" (customize-set-variable 'vhdl-compose-create-files 'single) :style radio :selected (eq 'single vhdl-compose-create-files)] ["Separate" (customize-set-variable 'vhdl-compose-create-files 'separate) :style radio :selected (eq 'separate vhdl-compose-create-files)]) ["Create Configuration File" (customize-set-variable 'vhdl-compose-configuration-create-file (not vhdl-compose-configuration-create-file)) :style toggle :selected vhdl-compose-configuration-create-file] ["Hierarchical Configuration" (customize-set-variable 'vhdl-compose-configuration-hierarchical (not vhdl-compose-configuration-hierarchical)) :style toggle :selected vhdl-compose-configuration-hierarchical] ["Use Subconfiguration" (customize-set-variable 'vhdl-compose-configuration-use-subconfiguration (not vhdl-compose-configuration-use-subconfiguration)) :style toggle :selected vhdl-compose-configuration-use-subconfiguration] "--" ["Customize Group..." (customize-group 'vhdl-compose) t]) ("Comment" ["Self Insert Comments" (customize-set-variable 'vhdl-self-insert-comments (not vhdl-self-insert-comments)) :style toggle :selected vhdl-self-insert-comments] ["Prompt for Comments" (customize-set-variable 'vhdl-prompt-for-comments (not vhdl-prompt-for-comments)) :style toggle :selected vhdl-prompt-for-comments] ["Inline Comment Column..." (customize-option 'vhdl-inline-comment-column) t] ["End Comment Column..." (customize-option 'vhdl-end-comment-column) t] "--" ["Customize Group..." (customize-group 'vhdl-comment) t]) ("Beautify" ["Auto Align Templates" (customize-set-variable 'vhdl-auto-align (not vhdl-auto-align)) :style toggle :selected vhdl-auto-align] ["Align Line Groups" (customize-set-variable 'vhdl-align-groups (not vhdl-align-groups)) :style toggle :selected vhdl-align-groups] ["Group Separation String..." (customize-option 'vhdl-align-group-separate) t] ["Align Lines with Same Indent" (customize-set-variable 'vhdl-align-same-indent (not vhdl-align-same-indent)) :style toggle :selected vhdl-align-same-indent] ["Beautify Options..." (customize-option 'vhdl-beautify-options) t] "--" ["Customize Group..." (customize-group 'vhdl-beautify) t]) ("Highlight" ["Highlighting On/Off..." (customize-option (if (fboundp 'global-font-lock-mode) 'global-font-lock-mode 'font-lock-auto-fontify)) t] ["Highlight Keywords" (progn (customize-set-variable 'vhdl-highlight-keywords (not vhdl-highlight-keywords)) (vhdl-fontify-buffer)) :style toggle :selected vhdl-highlight-keywords] ["Highlight Names" (progn (customize-set-variable 'vhdl-highlight-names (not vhdl-highlight-names)) (vhdl-fontify-buffer)) :style toggle :selected vhdl-highlight-names] ["Highlight Special Words" (progn (customize-set-variable 'vhdl-highlight-special-words (not vhdl-highlight-special-words)) (vhdl-fontify-buffer)) :style toggle :selected vhdl-highlight-special-words] ["Highlight Forbidden Words" (progn (customize-set-variable 'vhdl-highlight-forbidden-words (not vhdl-highlight-forbidden-words)) (vhdl-fontify-buffer)) :style toggle :selected vhdl-highlight-forbidden-words] ["Highlight Verilog Keywords" (progn (customize-set-variable 'vhdl-highlight-verilog-keywords (not vhdl-highlight-verilog-keywords)) (vhdl-fontify-buffer)) :style toggle :selected vhdl-highlight-verilog-keywords] ["Highlight \"translate_off\"" (progn (customize-set-variable 'vhdl-highlight-translate-off (not vhdl-highlight-translate-off)) (vhdl-fontify-buffer)) :style toggle :selected vhdl-highlight-translate-off] ["Case Sensitive Highlighting" (progn (customize-set-variable 'vhdl-highlight-case-sensitive (not vhdl-highlight-case-sensitive)) (vhdl-fontify-buffer)) :style toggle :selected vhdl-highlight-case-sensitive] ["Special Syntax Definition..." (customize-option 'vhdl-special-syntax-alist) t] ["Forbidden Words..." (customize-option 'vhdl-forbidden-words) t] ["Forbidden Syntax..." (customize-option 'vhdl-forbidden-syntax) t] ["Directive Keywords..." (customize-option 'vhdl-directive-keywords) t] ["Colors..." (customize-group 'vhdl-highlight-faces) t] "--" ["Customize Group..." (customize-group 'vhdl-highlight) t]) ("Speedbar" ["Auto Open at Startup" (customize-set-variable 'vhdl-speedbar-auto-open (not vhdl-speedbar-auto-open)) :style toggle :selected vhdl-speedbar-auto-open] ("Default Displaying Mode" ["Files" (customize-set-variable 'vhdl-speedbar-display-mode 'files) :style radio :selected (eq 'files vhdl-speedbar-display-mode)] ["Directory Hierarchy" (customize-set-variable 'vhdl-speedbar-display-mode 'directory) :style radio :selected (eq 'directory vhdl-speedbar-display-mode)] ["Project Hierarchy" (customize-set-variable 'vhdl-speedbar-display-mode 'project) :style radio :selected (eq 'project vhdl-speedbar-display-mode)]) ["Indentation Offset..." (customize-option 'speedbar-indentation-width) t] ["Scan Size Limits..." (customize-option 'vhdl-speedbar-scan-limit) t] ["Jump to Unit when Opening" (customize-set-variable 'vhdl-speedbar-jump-to-unit (not vhdl-speedbar-jump-to-unit)) :style toggle :selected vhdl-speedbar-jump-to-unit] ["Update Hierarchy on File Saving" (customize-set-variable 'vhdl-speedbar-update-on-saving (not vhdl-speedbar-update-on-saving)) :style toggle :selected vhdl-speedbar-update-on-saving] ("Save in Cache File" ["Hierarchy Information" (customize-set-variable 'vhdl-speedbar-save-cache (if (memq 'hierarchy vhdl-speedbar-save-cache) (delq 'hierarchy vhdl-speedbar-save-cache) (cons 'hierarchy vhdl-speedbar-save-cache))) :style toggle :selected (memq 'hierarchy vhdl-speedbar-save-cache)] ["Displaying Status" (customize-set-variable 'vhdl-speedbar-save-cache (if (memq 'display vhdl-speedbar-save-cache) (delq 'display vhdl-speedbar-save-cache) (cons 'display vhdl-speedbar-save-cache))) :style toggle :selected (memq 'display vhdl-speedbar-save-cache)]) ["Cache File Name..." (customize-option 'vhdl-speedbar-cache-file-name) t] "--" ["Customize Group..." (customize-group 'vhdl-speedbar) t]) ("Menu" ["Add Index Menu when Loading File" (progn (customize-set-variable 'vhdl-index-menu (not vhdl-index-menu)) (vhdl-index-menu-init)) :style toggle :selected vhdl-index-menu] ["Add Source File Menu when Loading File" (progn (customize-set-variable 'vhdl-source-file-menu (not vhdl-source-file-menu)) (vhdl-add-source-files-menu)) :style toggle :selected vhdl-source-file-menu] ["Add Hideshow Menu at Startup" (progn (customize-set-variable 'vhdl-hideshow-menu (not vhdl-hideshow-menu)) (vhdl-activate-customizations)) :style toggle :selected vhdl-hideshow-menu] ["Hide Everything Initially" (customize-set-variable 'vhdl-hide-all-init (not vhdl-hide-all-init)) :style toggle :selected vhdl-hide-all-init] "--" ["Customize Group..." (customize-group 'vhdl-menu) t]) ("Print" ["In Two Column Format" (progn (customize-set-variable 'vhdl-print-two-column (not vhdl-print-two-column)) (message "Activate new setting by saving options and restarting Emacs")) :style toggle :selected vhdl-print-two-column] ["Use Customized Faces" (progn (customize-set-variable 'vhdl-print-customize-faces (not vhdl-print-customize-faces)) (message "Activate new setting by saving options and restarting Emacs")) :style toggle :selected vhdl-print-customize-faces] "--" ["Customize Group..." (customize-group 'vhdl-print) t]) ("Miscellaneous" ["Use Intelligent Tab" (progn (customize-set-variable 'vhdl-intelligent-tab (not vhdl-intelligent-tab)) (vhdl-activate-customizations)) :style toggle :selected vhdl-intelligent-tab] ["Indent Syntax-Based" (customize-set-variable 'vhdl-indent-syntax-based (not vhdl-indent-syntax-based)) :style toggle :selected vhdl-indent-syntax-based] ["Indent Comments Like Next Code Line" (customize-set-variable 'vhdl-indent-comment-like-next-code-line (not vhdl-indent-comment-like-next-code-line)) :style toggle :selected vhdl-indent-comment-like-next-code-line] ["Word Completion is Case Sensitive" (customize-set-variable 'vhdl-word-completion-case-sensitive (not vhdl-word-completion-case-sensitive)) :style toggle :selected vhdl-word-completion-case-sensitive] ["Word Completion in Minibuffer" (progn (customize-set-variable 'vhdl-word-completion-in-minibuffer (not vhdl-word-completion-in-minibuffer)) (message "Activate new setting by saving options and restarting Emacs")) :style toggle :selected vhdl-word-completion-in-minibuffer] ["Underscore is Part of Word" (progn (customize-set-variable 'vhdl-underscore-is-part-of-word (not vhdl-underscore-is-part-of-word)) (vhdl-activate-customizations)) :style toggle :selected vhdl-underscore-is-part-of-word] "--" ["Customize Group..." (customize-group 'vhdl-misc) t]) ["Related..." (customize-browse 'vhdl-related) t] "--" ["Save Options" customize-save-customized t] ["Activate Options" vhdl-activate-customizations t] ["Browse Options..." vhdl-customize t])] 52 (#$ . 117150)])#@17 VHDL Mode menu. (defvar vhdl-mode-menu-list (vhdl-create-mode-menu) (#$ . 151618))#@24 Update VHDL Mode menu. (defalias 'vhdl-update-mode-menu #[0 "\302 \303\304\305\306#\210\307\304 \306$\207" [vhdl-mode-menu-list vhdl-mode-map vhdl-create-mode-menu defvar-1 vhdl-mode-menu nil "Menu keymap for VHDL Mode." easy-menu-do-define] 5 (#$ . 151706) nil])#@74 Imenu generic expression for VHDL Mode. See `imenu-generic-expression'. (defconst vhdl-imenu-generic-expression '(("Subprogram" "^\\s-*\\(\\(\\(impure\\|pure\\)\\s-+\\|\\)function\\|procedure\\)\\s-+\\(\"?\\(\\w\\|\\s_\\)+\"?\\)" 4) ("Instance" "^\\s-*\\(\\(\\w\\|\\s_\\)+\\s-*:\\(\\s-\\|\n\\)*\\(entity\\s-+\\(\\w\\|\\s_\\)+\\.\\)?\\(\\w\\|\\s_\\)+\\)\\(\\s-\\|\n\\)+\\(generic\\|port\\)\\s-+map\\>" 1) ("Component" "^\\s-*\\(component\\)\\s-+\\(\\(\\w\\|\\s_\\)+\\)" 2) ("Procedural" "^\\s-*\\(\\(\\w\\|\\s_\\)+\\)\\s-*:\\(\\s-\\|\n\\)*\\(procedural\\)" 1) ("Process" "^\\s-*\\(\\(\\w\\|\\s_\\)+\\)\\s-*:\\(\\s-\\|\n\\)*\\(\\(postponed\\s-+\\|\\)process\\)" 1) ("Block" "^\\s-*\\(\\(\\w\\|\\s_\\)+\\)\\s-*:\\(\\s-\\|\n\\)*\\(block\\)" 1) ("Package" "^\\s-*\\(package\\( body\\|\\)\\)\\s-+\\(\\(\\w\\|\\s_\\)+\\)" 3) ("Configuration" "^\\s-*\\(configuration\\)\\s-+\\(\\(\\w\\|\\s_\\)+\\s-+of\\s-+\\(\\w\\|\\s_\\)+\\)" 2) ("Architecture" "^\\s-*\\(architecture\\)\\s-+\\(\\(\\w\\|\\s_\\)+\\s-+of\\s-+\\(\\w\\|\\s_\\)+\\)" 2) ("Entity" "^\\s-*\\(entity\\)\\s-+\\(\\(\\w\\|\\s_\\)+\\)" 2) ("Context" "^\\s-*\\(context\\)\\s-+\\(\\(\\w\\|\\s_\\)+\\)" 2)) (#$ . 151977))#@24 Initialize index menu. (defalias 'vhdl-index-menu-init #[0 "\304\300!\210\305\304\302!\210  \205�\306\307!\205�\310\311!\207" [imenu-case-fold-search vhdl-imenu-generic-expression imenu-generic-expression vhdl-index-menu make-local-variable t fboundp imenu imenu-add-to-menubar "Index"] 2 (#$ . 153151)]) (defvar vhdl-sources-menu nil)#@116 Call `directory-files' if DIRECTORY exists, otherwise generate error message. (fn DIRECTORY &optional FULL MATCH) (defalias 'vhdl-directory-files #[769 "\300!\204 �\301\302\"\207\303#\304\305\"\262\304\306\"\207" [file-directory-p vhdl-warning-when-idle "No such directory: \"%s\"" directory-files delete "." ".."] 7 (#$ . 153497)])#@97 Get list of VHDL source files in DIRECTORY or current directory. (fn &optional FULL DIRECTORY) (defalias 'vhdl-get-source-files #[512 "\302\303\262\203 �@A\304=\203�\211@@\305Q\262A\262\202�\211\306\307\310\"O\311P\262\312\2061� #\207" [auto-mode-alist default-directory nil "\\`[^.].*\\(" vhdl-mode "\\|" 0 string-match "\\\\|$" "\\)" vhdl-directory-files] 9 (#$ . 153844)])#@114 Scan directory for all VHDL source files and generate menu. The directory of the current source file is scanned. (defalias 'vhdl-add-source-files-menu #[0 "\300\301!\210\302 \303 \304\211\211\262\203(�\305\262\306@\307@D\305#B\262A\262\202 �\310\311\"\262\211\2037�\312B\262\313B\262\311B\262\314\315\304\316#\210\317\315\316$\266\300\320!\207" [message "Scanning directory for source files ..." current-local-map vhdl-get-source-files nil t vector find-file vhdl-menu-split "Sources" "--" ["*Rescan*" vhdl-add-source-files-menu t] defvar-1 vhdl-sources-menu "VHDL source files menu" easy-menu-do-define ""] 9 (#$ . 154242) nil]) (defvar vhdl-mode-hook nil) (byte-code "\300\301N\204\f�\302\300\301\303#\210\304\305!\204�\302\305\306\307#\210\300\207" [vhdl-mode-hook variable-documentation put "Hook run after entering '(VHDL (vhdl-electric-mode / (vhdl-stutter-mode /)) (vhdl-electric-mode e) (vhdl-stutter-mode s)) mode.\nNo problems result if this variable is not bound.\n`add-hook' automatically binds it. (This is true for all hook variables.)" boundp vhdl-mode-map definition-name vhdl-mode] 4) (defvar vhdl-mode-map (make-sparse-keymap)) (byte-code "\300\301N\204�\302\300\301\303\304!#\210\305\306!\204*�\302\306\307\310#\210\311\306\305\306!\203&�\312\202(�\313 \"\210\306\301N\2048�\302\306\301\303\314!#\210\302\310\315\316#\207" [vhdl-mode-map variable-documentation put purecopy "Keymap for `vhdl-mode'." boundp vhdl-mode-syntax-table definition-name vhdl-mode defvar-1 nil make-syntax-table "Syntax table for `vhdl-mode'." derived-mode-parent prog-mode] 5)#@25674 Major mode for editing VHDL code. Usage: ------ TEMPLATE INSERTION (electrification): After typing a VHDL keyword and entering `SPC', you are prompted for arguments while a template is generated for that VHDL construct. Typing `RET' or `C-g' at the first (mandatory) prompt aborts the current template generation. Optional arguments are indicated by square brackets and removed if the queried string is left empty. Prompts for mandatory arguments remain in the code if the queried string is left empty. They can be queried again by `C-c C-t C-q'. Enabled electrification is indicated by `/e' in the mode line. Typing `M-SPC' after a keyword inserts a space without calling the template generator. Automatic template generation (i.e. electrification) can be disabled (enabled) by typing `C-c C-m C-e' or by setting option `vhdl-electric-mode' (see OPTIONS). Template generators can be invoked from the VHDL menu, by key bindings, by typing `C-c C-i C-c' and choosing a construct, or by typing the keyword (i.e. first word of menu entry not in parenthesis) and `SPC'. The following abbreviations can also be used: arch, attr, cond, conf, comp, cons, func, inst, pack, sig, var. Template styles can be customized in customization group `vhdl-template' (see OPTIONS). HEADER INSERTION: A file header can be inserted by `C-c C-t C-h'. A file footer (template at the end of the file) can be inserted by `C-c C-t C-f'. See customization group `vhdl-header'. STUTTERING: Double striking of some keys inserts cumbersome VHDL syntax elements. Stuttering can be disabled (enabled) by typing `C-c C-m C-s' or by option `vhdl-stutter-mode'. Enabled stuttering is indicated by `/s' in the mode line. The stuttering keys and their effects are: ;; --> " : " [ --> ( -- --> comment ;;; --> " := " [[ --> [ --CR --> comment-out code .. --> " => " ] --> ) --- --> horizontal line ,, --> " <= " ]] --> ] ---- --> display comment == --> " == " \='\=' --> \" WORD COMPLETION: Typing `TAB' after a (not completed) word looks for a VHDL keyword or a word in the buffer that starts alike, inserts it and adjusts case. Re-typing `TAB' toggles through alternative word completions. This also works in the minibuffer (i.e. in template generator prompts). Typing `TAB' after `(' looks for and inserts complete parenthesized expressions (e.g. for array index ranges). All keywords as well as standard types and subprograms of VHDL have predefined abbreviations (e.g., type "std" and `TAB' will toggle through all standard types beginning with "std"). Typing `TAB' after a non-word character indents the line if at the beginning of a line (i.e. no preceding non-blank characters), and inserts a tabulator stop otherwise. `M-TAB' always inserts a tabulator stop. COMMENTS: `--' puts a single comment. `---' draws a horizontal line for separating code segments. `----' inserts a display comment, i.e. two horizontal lines with a comment in between. `--CR' comments out code on that line. Re-hitting CR comments out following lines. `C-c C-c' comments out a region if not commented out, uncomments a region if already commented out. Option `comment-style' defines where the comment characters should be placed (beginning of line, indent, etc.). You are prompted for comments after object definitions (i.e. signals, variables, constants, ports) and after subprogram and process specifications if option `vhdl-prompt-for-comments' is non-nil. Comments are automatically inserted as additional labels (e.g. after begin statements) and as help comments if `vhdl-self-insert-comments' is non-nil. Inline comments (i.e. comments after a piece of code on the same line) are indented at least to `vhdl-inline-comment-column'. Comments go at maximum to `vhdl-end-comment-column'. `RET' after a space in a comment will open a new comment line. Typing beyond `vhdl-end-comment-column' in a comment automatically opens a new comment line. `M-q' re-fills multi-line comments. INDENTATION: `TAB' indents a line if at the beginning of the line. The amount of indentation is specified by option `vhdl-basic-offset'. `C-c C-i C-l' always indents the current line (is bound to `TAB' if option `vhdl-intelligent-tab' is nil). If a region is active, `TAB' indents the entire region. Indentation can be done for a group of lines (`C-c C-i C-g'), a region (`M-C-\') or the entire buffer (menu). Argument and port lists are indented normally (nil) or relative to the opening parenthesis (non-nil) according to option `vhdl-argument-list-indent'. If option `vhdl-indent-tabs-mode' is nil, spaces are used instead of tabs. `\[tabify]' and `\[untabify]' allow the conversion of spaces to tabs and vice versa. Syntax-based indentation can be very slow in large files. Option `vhdl-indent-syntax-based' allows you to use faster but simpler indentation. Option `vhdl-indent-comment-like-next-code-line' controls whether comment lines are indented like the preceding or like the following code line. ALIGNMENT: The alignment functions align operators, keywords, and inline comments to beautify the code. `C-c C-a C-a' aligns a group of consecutive lines separated by blank lines, `C-c C-a C-i' a block of lines with same indent. `C-c C-a C-l' aligns all lines belonging to a list enclosed by a pair of parentheses (e.g. port clause/map, argument list), and `C-c C-a C-d' all lines within the declarative part of a design unit. `C-c C-a M-a' aligns an entire region. `C-c C-a C-c' aligns inline comments for a group of lines, and `C-c C-a M-c' for a region. If option `vhdl-align-groups' is non-nil, groups of code lines separated by special lines (see option `vhdl-align-group-separate') are aligned individually. If option `vhdl-align-same-indent' is non-nil, blocks of lines with same indent are aligned separately. Some templates are automatically aligned after generation if option `vhdl-auto-align' is non-nil. Alignment tries to align inline comments at `vhdl-inline-comment-column' and tries inline comment not to exceed `vhdl-end-comment-column'. `C-c C-x M-w' fixes up whitespace in a region. That is, operator symbols are surrounded by one space, and multiple spaces are eliminated. CODE FILLING: Code filling allows you to condense code (e.g. sensitivity lists or port maps) by removing comments and newlines and re-wrapping so that all lines are maximally filled (block filling). `C-c C-f C-f' fills a list enclosed by parenthesis, `C-c C-f C-g' a group of lines separated by blank lines, `C-c C-f C-i' a block of lines with same indent, and `C-c C-f M-f' an entire region. CODE BEAUTIFICATION: `C-c M-b' and `C-c C-b' beautify the code of a region or of the entire buffer respectively. This includes indentation, alignment, and case fixing. Code beautification can also be run non-interactively using the command: emacs -batch -l ~/.emacs filename.vhd -f vhdl-beautify-buffer PORT TRANSLATION: Generic and port clauses from entity or component declarations can be copied (`C-c C-p C-w') and pasted as entity and component declarations, as component instantiations and corresponding internal constants and signals, as a generic map with constants as actual generics, and as internal signal initializations (menu). To include formals in component instantiations, see option `vhdl-association-list-with-formals'. To include comments in pasting, see options `vhdl-include-...-comments'. A clause with several generic/port names on the same line can be flattened (`C-c C-p C-f') so that only one name per line exists. The direction of ports can be reversed (`C-c C-p C-r'), i.e., inputs become outputs and vice versa, which can be useful in testbenches. (This reversion is done on the internal data structure and is only reflected in subsequent paste operations.) Names for actual ports, instances, testbenches, and design-under-test instances can be derived from existing names according to options `vhdl-...-name'. See customization group `vhdl-port'. SUBPROGRAM TRANSLATION: Similar functionality exists for copying/pasting the interface of subprograms (function/procedure). A subprogram interface can be copied and then pasted as a subprogram declaration, body or call (uses association list with formals). TESTBENCH GENERATION: A copied port can also be pasted as a testbench. The generated testbench includes an entity, an architecture, and an optional configuration. The architecture contains the component declaration and instantiation of the DUT as well as internal constant and signal declarations. Additional user-defined templates can be inserted. The names used for entity/architecture/configuration/DUT as well as the file structure to be generated can be customized. See customization group `vhdl-testbench'. KEY BINDINGS: Key bindings (`C-c ...') exist for most commands (see in menu). VHDL MENU: All commands can be found in the VHDL menu including their key bindings. FILE BROWSER: The speedbar allows browsing of directories and file contents. It can be accessed from the VHDL menu and is automatically opened if option `vhdl-speedbar-auto-open' is non-nil. In speedbar, open files and directories with `mouse-2' on the name and browse/rescan their contents with `mouse-2'/`S-mouse-2' on the `+'. DESIGN HIERARCHY BROWSER: The speedbar can also be used for browsing the hierarchy of design units contained in the source files of the current directory or the specified projects (see option `vhdl-project-alist'). The speedbar can be switched between file, directory hierarchy and project hierarchy browsing mode in the speedbar menu or by typing `f', `h' or `H' in speedbar. In speedbar, open design units with `mouse-2' on the name and browse their hierarchy with `mouse-2' on the `+'. Ports can directly be copied from entities and components (in packages). Individual design units and complete designs can directly be compiled ("Make" menu entry). The hierarchy is automatically updated upon saving a modified source file when option `vhdl-speedbar-update-on-saving' is non-nil. The hierarchy is only updated for projects that have been opened once in the speedbar. The hierarchy is cached between Emacs sessions in a file (see options in group `vhdl-speedbar'). Simple design consistency checks are done during scanning, such as multiple declarations of the same unit or missing primary units that are required by secondary units. STRUCTURAL COMPOSITION: Enables simple structural composition. `C-c C-m C-n' creates a skeleton for a new component. Subcomponents (i.e. component declaration and instantiation) can be automatically placed from a previously read port (`C-c C-m C-p') or directly from the hierarchy browser (`P'). Finally, all subcomponents can be automatically connected using internal signals and ports (`C-c C-m C-w') following these rules: - subcomponent actual ports with same name are considered to be connected by a signal (internal signal or port) - signals that are only inputs to subcomponents are considered as inputs to this component -> input port created - signals that are only outputs from subcomponents are considered as outputs from this component -> output port created - signals that are inputs to AND outputs from subcomponents are considered as internal connections -> internal signal created Purpose: With appropriate naming conventions it is possible to create higher design levels with only a few mouse clicks or key strokes. A new design level can be created by simply generating a new component, placing the required subcomponents from the hierarchy browser, and wiring everything automatically. Note: Automatic wiring only works reliably on templates of new components and component instantiations that were created by VHDL mode. Component declarations can be placed in a components package (option `vhdl-use-components-package') which can be automatically generated for an entire directory or project (`C-c C-m M-p'). The VHDL'93 direct component instantiation is also supported (option `vhdl-use-direct-instantiation'). Configuration declarations can automatically be generated either from the menu (`C-c C-m C-f') (for the architecture the cursor is in) or from the speedbar menu (for the architecture under the cursor). The configurations can optionally be hierarchical (i.e. include all component levels of a hierarchical design, option `vhdl-compose-configuration-hierarchical') or include subconfigurations (option `vhdl-compose-configuration-use-subconfiguration'). For subcomponents in hierarchical configurations, the most-recently-analyzed (mra) architecture is selected. If another architecture is desired, it can be marked as most-recently-analyzed (speedbar menu) before generating the configuration. Note: Configurations of subcomponents (i.e. hierarchical configuration declarations) are currently not considered when displaying configurations in speedbar. See the options group `vhdl-compose' for all relevant user options. SOURCE FILE COMPILATION: The syntax of the current buffer can be analyzed by calling a VHDL compiler (menu, `C-c C-k'). The compiler to be used is specified by option `vhdl-compiler'. The available compilers are listed in option `vhdl-compiler-alist' including all required compilation command, command options, compilation directory, and error message syntax information. New compilers can be added. All the source files of an entire design can be compiled by the `make' command (menu, `C-c M-C-k') if an appropriate Makefile exists. MAKEFILE GENERATION: Makefiles can be generated automatically by an internal generation routine (`C-c M-k'). The library unit dependency information is obtained from the hierarchy browser. Makefile generation can be customized for each compiler in option `vhdl-compiler-alist'. Makefile generation can also be run non-interactively using the command: emacs -batch -l ~/.emacs -l vhdl-mode [-compiler compilername] [-project projectname] -f vhdl-generate-makefile The Makefile's default target "all" compiles the entire design, the target "clean" removes it and the target "library" creates the library directory if not existent. These target names can be customized by option `vhdl-makefile-default-targets'. The Makefile also includes a target for each primary library unit which allows selective compilation of this unit, its secondary units and its subhierarchy (example: compilation of a design specified by a configuration). User specific parts can be inserted into a Makefile with option `vhdl-makefile-generation-hook'. Limitations: - Only library units and dependencies within the current library are considered. Makefiles for designs that span multiple libraries are not (yet) supported. - Only one-level configurations are supported (also hierarchical), but configurations that go down several levels are not. - The "others" keyword in configurations is not supported. PROJECTS: Projects can be defined in option `vhdl-project-alist' and a current project be selected using option `vhdl-project' (permanently) or from the menu or speedbar (temporarily). For each project, title and description strings (for the file headers), source files/directories (for the hierarchy browser and Makefile generation), library name, and compiler-dependent options, exceptions and compilation directory can be specified. Compilation settings overwrite the settings of option `vhdl-compiler-alist'. Project setups can be exported (i.e. written to a file) and imported. Imported setups are not automatically saved in `vhdl-project-alist' but can be saved afterwards in its customization buffer. When starting Emacs with VHDL Mode (i.e. load a VHDL file or use "emacs -l vhdl-mode") in a directory with an existing project setup file, it is automatically loaded and its project activated if option `vhdl-project-autoload' is non-nil. Names/paths of the project setup files can be specified in option `vhdl-project-file-name'. Multiple project setups can be automatically loaded from global directories. This is an alternative to specifying project setups with option `vhdl-project-alist'. SPECIAL MENUS: As an alternative to the speedbar, an index menu can be added (set option `vhdl-index-menu' to non-nil) or made accessible as a mouse menu (e.g. add "(global-set-key [S-down-mouse-3] \='imenu)" to your start-up file) for browsing the file contents (is not populated if buffer is larger than 256000). Also, a source file menu can be added (set option `vhdl-source-file-menu' to non-nil) for browsing the current directory for VHDL source files. VHDL STANDARDS: The VHDL standards to be used are specified in option `vhdl-standard'. Available standards are: VHDL'87/'93(02)/'08, VHDL-AMS, and Math Packages. KEYWORD CASE: Lower and upper case for keywords and standardized types, attributes, and enumeration values is supported. If the option `vhdl-upper-case-keywords' is set to non-nil, keywords can be typed in lower case and are converted into upper case automatically (not for types, attributes, and enumeration values). The case of keywords, types, attributes,and enumeration values can be fixed for an entire region (menu) or buffer (`C-c C-x C-c') according to the options `vhdl-upper-case-{keywords,types,attributes,enum-values}'. HIGHLIGHTING (fontification): Keywords and standardized types, attributes, enumeration values, and function names (controlled by option `vhdl-highlight-keywords'), as well as comments, strings, and template prompts are highlighted using different colors. Unit, subprogram, signal, variable, constant, parameter and generic/port names in declarations as well as labels are highlighted if option `vhdl-highlight-names' is non-nil. Additional reserved words or words with a forbidden syntax (e.g. words that should be avoided) can be specified in option `vhdl-forbidden-words' or `vhdl-forbidden-syntax' and be highlighted in a warning color (option `vhdl-highlight-forbidden-words'). Verilog keywords are highlighted as forbidden words if option `vhdl-highlight-verilog-keywords' is non-nil. Words with special syntax can be highlighted by specifying their syntax and color in option `vhdl-special-syntax-alist' and by setting option `vhdl-highlight-special-words' to non-nil. This allows you to establish some naming conventions (e.g. to distinguish different kinds of signals or other objects by using name suffices) and to support them visually. Option `vhdl-highlight-case-sensitive' can be set to non-nil in order to support case-sensitive highlighting. However, keywords are then only highlighted if written in lower case. Code between "translate_off" and "translate_on" pragmas is highlighted using a different background color if option `vhdl-highlight-translate-off' is non-nil. For documentation and customization of the used colors see customization group `vhdl-highlight-faces' (`\[customize-group]'). For highlighting of matching parenthesis, see customization group `paren-showing'. Automatic buffer highlighting is turned on/off by option `global-font-lock-mode' (`font-lock-auto-fontify' in XEmacs). USER MODELS: VHDL models (templates) can be specified by the user and made accessible in the menu, through key bindings (`C-c C-m ...'), or by keyword electrification. See option `vhdl-model-alist'. HIDE/SHOW: The code of blocks, processes, subprograms, component declarations and instantiations, generic/port clauses, and configuration declarations can be hidden using the `Hide/Show' menu or by pressing `S-mouse-2' within the code (see customization group `vhdl-menu'). XEmacs: limited functionality due to old `hideshow.el' package. CODE UPDATING: - Sensitivity List: `C-c C-u C-s' updates the sensitivity list of the current process, `C-c C-u M-s' of all processes in the current buffer. Limitations: - Only declared local signals (ports, signals declared in architecture and blocks) are automatically inserted. - Global signals declared in packages are not automatically inserted. Insert them once manually (will be kept afterwards). - Out parameters of procedures are considered to be read. Use option `vhdl-entity-file-name' to specify the entity file name (used to obtain the port names). Use option `vhdl-array-index-record-field-in-sensitivity-list' to specify whether to include array indices and record fields in sensitivity lists. CODE FIXING: `C-c C-x C-p' fixes the closing parenthesis of a generic/port clause (e.g., if the closing parenthesis is on the wrong line or is missing). PRINTING: PostScript printing with different faces (an optimized set of faces is used if `vhdl-print-customize-faces' is non-nil) or colors (if `ps-print-color-p' is non-nil) is possible using the standard Emacs PostScript printing commands. Option `vhdl-print-two-column' defines appropriate default settings for nice landscape two-column printing. The paper format can be set by option `ps-paper-type'. Do not forget to switch `ps-print-color-p' to nil for printing on black-and-white printers. OPTIONS: User options allow customization of VHDL Mode. All options are accessible from the "Options" menu entry. Simple options (switches and choices) can directly be changed, while for complex options a customization buffer is opened. Changed options can be saved for future sessions using the "Save Options" menu entry. Options and their detailed descriptions can also be accessed by using the "Customize" menu entry or the command `\[customize-option]' (`\[customize-group]' for groups). Some customizations only take effect after some action (read the NOTE in the option documentation). Customization can also be done globally (i.e. site-wide, read the INSTALL file). Not all options are described in this documentation, so go and see what other useful user options there are (`\[vhdl-customize]' or menu)! FILE EXTENSIONS: As default, files with extensions ".vhd" and ".vhdl" are automatically recognized as VHDL source files. To add an extension ".xxx", add the following line to your Emacs start-up file (`.emacs'): (push \='("\\.xxx\\\='" . vhdl-mode) auto-mode-alist) HINTS: - To start Emacs with open VHDL hierarchy browser without having to load a VHDL file first, use the command: emacs -l vhdl-mode -f speedbar-frame-mode - Type `C-g C-g' to interrupt long operations or if Emacs hangs. - Some features only work on properly indented code. RELEASE NOTES: See also the release notes (menu) for added features in new releases. Maintenance: ------------ To submit a bug report, enter `\[vhdl-submit-bug-report]' within VHDL Mode. Add a description of the problem and include a reproducible test case. Questions and enhancement requests can be sent to <reto@gnu.org>. The `vhdl-mode-announce' mailing list informs about new VHDL Mode releases. The `vhdl-mode-victims' mailing list informs about new VHDL Mode beta releases. You are kindly invited to participate in beta testing. Subscribe to above mailing lists by sending an email to <reto@gnu.org>. VHDL Mode is officially distributed at https://guest.iis.ee.ethz.ch/~zimmi/emacs/vhdl-mode.html where the latest version can be found. Known problems: --------------- - XEmacs: Incorrect start-up when automatically opening speedbar. - XEmacs: Indentation in XEmacs 21.4 (and higher). - Indentation incorrect for new `postponed' VHDL keyword. - Indentation incorrect for `protected body' construct. The VHDL Mode Authors Reto Zimmermann and Rod Whitby Key bindings: ------------- \{vhdl-mode-map} In addition to any hooks its parent mode `prog-mode' might have run, this mode runs the hook `vhdl-mode-hook', as the final or penultimate step during initialization. (defalias 'vhdl-mode #[0 "\306\300!\210\307\310 \210\311\312\310\313N\203�\314\311\313\310\313N#\210\315 !\204'�\316 \317 \"\210\320\f!\211\2035�\211\321 =\203;�\322\f\323 \"\210\210\324 !\210\325\f!\210 @\306\326!\210\327\306\330!\210\306\331!\210\307\306\332!\210\307\306\333!\210\334\306\335!\210\336\306\337!\210\340\306\341!\210A!\306\342!\210B\"\306\343!\210\344#\306\345!\210\346%\306\347!\210C'\306\350!\210\346(\351\352!\203\263�\306\352!\210\353*\306\354!\210\355\346D?\356\357\257,\306\360!\210\3610E\203\334�\306\362!\210\3462\306\363!\210\3463\364 \210F\203\347�\365 \210\366\367\346\370#\210\371\367 \370G$\210\372 \210\373\374!\210\375 \210\376 \210\377\201J�HI\203\340\202\201K�#)\210\201L�\201M�!\207" [delay-mode-hooks major-mode mode-name vhdl-mode-map vhdl-mode-syntax-table vhdl-mode-abbrev-table make-local-variable t prog-mode vhdl-mode ("VHDL" (vhdl-electric-mode "/" (vhdl-stutter-mode "/")) (vhdl-electric-mode "e") (vhdl-stutter-mode "s")) mode-class put keymap-parent set-keymap-parent current-local-map char-table-parent standard-syntax-table set-char-table-parent syntax-table use-local-map set-syntax-table paragraph-start "\\s-*\\(--+\\s-*$\\|$\\)" paragraph-separate paragraph-ignore-fill-prefix parse-sexp-ignore-comments indent-line-function vhdl-indent-line comment-start "--" comment-end "" comment-column end-comment-column comment-start-skip "--+\\s-*" comment-multi-line nil indent-tabs-mode hippie-expand-verbose boundp comment-indent-function vhdl-comment-indent font-lock-defaults (nil vhdl-font-lock-keywords) ((95 . "w")) beginning-of-line syntax-propertize-function #[514 "b\210`W\205:�\300\301\302#\205:�\303\224\204�\304\224\203�\303\224\203)�\305\303\224\303\225\306\307$\210\304\224\203�\305\304\224\304\225\306\310$\210\202�\207" [re-search-forward "\\('\\).\\('\\)" t 1 2 put-text-property syntax-table (7 . 39) (7 . 39)] 7 "\n\n(fn START END)"] compilation-error-regexp-alist compilation-file-regexp-alist vhdl-index-menu-init vhdl-add-source-files-menu defvar-1 vhdl-mode-menu "Menu keymap for VHDL Mode." easy-menu-do-define vhdl-hideshow-init run-hooks menu-bar-update-hook vhdl-ps-print-init vhdl-write-file-hooks-init message local-abbrev-table vhdl-inline-comment-column vhdl-end-comment-column vhdl-indent-tabs-mode vhdl-highlight-case-sensitive vhdl-compile-use-local-error-regexp vhdl-source-file-menu vhdl-mode-menu-list vhdl-version noninteractive "VHDL Mode %s.%s" " See menu for documentation and release notes." run-mode-hooks vhdl-mode-hook] 5 (#$ . 155845) nil])#@49 Activate all customizations on local variables. (defalias 'vhdl-activate-customizations #[0 "\306 \210\307!\210\310 !\210\n\f\311 \210\312 \210\313 \210\314\315!\207" [vhdl-mode-map vhdl-mode-syntax-table vhdl-inline-comment-column comment-column vhdl-end-comment-column end-comment-column vhdl-mode-map-init use-local-map set-syntax-table vhdl-write-file-hooks-init vhdl-update-mode-menu vhdl-hideshow-init run-hooks menu-bar-update-hook] 2 (#$ . 184109) nil])#@40 Add/remove hooks when buffer is saved. (defalias 'vhdl-write-file-hooks-init #[0 "\203�\301\302\303\304\305$\210\202�\306\302\303\305#\210\301\307\310\304\305$\207" [vhdl-modify-date-on-saving add-hook write-file-functions vhdl-template-modify-noerror nil t remove-hook after-save-hook vhdl-add-modified-file] 5 (#$ . 184579)])#@58 Process command line options for VHDL Mode. (fn OPTION) (defalias 'vhdl-process-command-line-option #[257 "\211\301\267\202�\302@!\210A\211\207\303@!\210A\211\207\304\207" [command-line-args-left #s(hash-table size 2 test equal rehash-size 1.5 rehash-threshold 0.8125 purecopy t data ("-compiler" 6 "-project" 16)) vhdl-set-compiler vhdl-set-project nil] 3 (#$ . 184915)]) (byte-code "\301\302\"\301\207" [command-switch-alist append (("-compiler" . vhdl-process-command-line-option) ("-project" . vhdl-process-command-line-option))] 3)#@27 List of VHDL'02 keywords. (defconst vhdl-02-keywords '("abs" "access" "after" "alias" "all" "and" "architecture" "array" "assert" "attribute" "begin" "block" "body" "buffer" "bus" "case" "component" "configuration" "constant" "disconnect" "downto" "else" "elsif" "end" "entity" "exit" "file" "for" "function" "generate" "generic" "group" "guarded" "if" "impure" "in" "inertial" "inout" "is" "label" "library" "linkage" "literal" "loop" "map" "mod" "nand" "new" "next" "nor" "not" "null" "of" "on" "open" "or" "others" "out" "package" "port" "postponed" "procedure" "process" "protected" "pure" "range" "record" "register" "reject" "rem" "report" "return" "rol" "ror" "select" "severity" "shared" "signal" "sla" "sll" "sra" "srl" "subtype" "then" "to" "transport" "type" "unaffected" "units" "until" "use" "variable" "wait" "when" "while" "with" "xnor" "xor") (#$ . 185467))#@27 List of VHDL'08 keywords. (defconst vhdl-08-keywords '("context" "force" "property" "release" "sequence") (#$ . 186346))#@28 List of VHDL-AMS keywords. (defconst vhdl-ams-keywords '("across" "break" "limit" "nature" "noise" "procedural" "quantity" "reference" "spectrum" "subnature" "terminal" "through" "tolerance") (#$ . 186472))#@70 List of Verilog keywords as candidate for additional reserved words. (defconst vhdl-verilog-keywords '("`define" "`else" "`endif" "`ifdef" "`include" "`timescale" "`undef" "always" "and" "assign" "begin" "buf" "bufif0" "bufif1" "case" "casex" "casez" "cmos" "deassign" "default" "defparam" "disable" "edge" "else" "end" "endattribute" "endcase" "endfunction" "endmodule" "endprimitive" "endspecify" "endtable" "endtask" "event" "for" "force" "forever" "fork" "function" "highz0" "highz1" "if" "initial" "inout" "input" "integer" "join" "large" "macromodule" "makefile" "medium" "module" "nand" "negedge" "nmos" "nor" "not" "notif0" "notif1" "or" "output" "parameter" "pmos" "posedge" "primitive" "pull0" "pull1" "pulldown" "pullup" "rcmos" "real" "realtime" "reg" "release" "repeat" "rnmos" "rpmos" "rtran" "rtranif0" "rtranif1" "scalared" "signed" "small" "specify" "specparam" "strength" "strong0" "strong1" "supply" "supply0" "supply1" "table" "task" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1" "triand" "trior" "trireg" "vectored" "wait" "wand" "weak0" "weak1" "while" "wire" "wor" "xnor" "xor") (#$ . 186684))#@37 List of VHDL'02 standardized types. (defconst vhdl-02-types '("boolean" "bit" "bit_vector" "character" "severity_level" "integer" "real" "time" "natural" "positive" "string" "line" "text" "side" "unsigned" "signed" "delay_length" "file_open_kind" "file_open_status" "std_logic" "std_logic_vector" "std_ulogic" "std_ulogic_vector") (#$ . 187814))#@37 List of VHDL'08 standardized types. (defconst vhdl-08-types '("boolean_vector" "integer_vector" "real_vector" "time_vector") (#$ . 188165))#@38 List of VHDL-AMS standardized types. (defconst vhdl-ams-types '("domain_type" "real_vector" "energy" "power" "periodicity" "real_across" "real_through" "unspecified" "unspecified_vector" "energy_vector" "power_vector" "periodicity_vector" "real_across_vector" "real_through_vector" "voltage" "current" "charge" "resistance" "conductance" "capacitance" "mmf" "electric_flux" "electric_flux_density" "electric_field_strength" "magnetic_flux" "magnetic_flux_density" "magnetic_field_strength" "inductance" "reluctance" "electrical" "electrical_vector" "magnetic" "magnetic_vector" "voltage_vector" "current_vector" "mmf_vector" "magnetic_flux_vector" "charge_vector" "resistance_vector" "conductance_vector" "capacitance_vector" "electric_flux_vector" "electric_flux_density_vector" "electric_field_strength_vector" "magnetic_flux_density_vector" "magnetic_field_strength_vector" "inductance_vector" "reluctance_vector" "ground" "displacement" "force" "velocity" "acceleration" "mass" "stiffness" "damping" "momentum" "angle" "torque" "angular_velocity" "angular_acceleration" "moment_inertia" "angular_momentum" "angular_stiffness" "angular_damping" "translational" "translational_vector" "translational_velocity" "translational_velocity_vector" "rotational" "rotational_vector" "rotational_velocity" "rotational_velocity_vector" "displacement_vector" "force_vector" "velocity_vector" "force_velocity_vector" "angle_vector" "torque_vector" "angular_velocity_vector" "torque_velocity_vector" "acceleration_vector" "mass_vector" "stiffness_vector" "damping_vector" "momentum_vector" "angular_acceleration_vector" "moment_inertia_vector" "angular_momentum_vector" "angular_stiffness_vector" "angular_damping_vector" "anchor" "translational_v_ref" "rotational_v_ref" "translational_v" "rotational_v" "illuminance" "luminous_flux" "luminous_intensity" "irradiance" "radiant" "radiant_vector" "luminous_intensity_vector" "luminous_flux_vector" "illuminance_vector" "irradiance_vector" "temperature" "heat_flow" "thermal_capacitance" "thermal_resistance" "thermal_conductance" "thermal" "thermal_vector" "temperature_vector" "heat_flow_vector" "thermal_capacitance_vector" "thermal_resistance_vector" "thermal_conductance_vector" "pressure" "vflow_rate" "mass_flow_rate" "volume" "density" "viscosity" "fresistance" "fconductance" "fcapacitance" "inertance" "cfresistance" "cfcapacitance" "cfinertance" "cfconductance" "fluidic" "fluidic_vector" "compressible_fluidic" "compressible_fluidic_vector" "pressure_vector" "vflow_rate_vector" "mass_flow_rate_vector" "volume_vector" "density_vector" "viscosity_vector" "fresistance_vector" "fconductance_vector" "fcapacitance_vector" "inertance_vector" "cfresistance_vector" "cfconductance_vector" "cfcapacitance_vector" "cfinertance_vector") (#$ . 188310))#@43 List of Math Packages standardized types. (defconst vhdl-math-types '("complex" "complex_polar" "positive_real" "principal_value") (#$ . 191108))#@42 List of VHDL'02 standardized attributes. (defconst vhdl-02-attributes '("base" "left" "right" "high" "low" "pos" "val" "succ" "pred" "leftof" "rightof" "range" "reverse_range" "length" "delayed" "stable" "quiet" "transaction" "event" "active" "last_event" "last_active" "last_value" "driving" "driving_value" "ascending" "value" "image" "simple_name" "instance_name" "path_name" "foreign") (#$ . 191259))#@42 List of VHDL'08 standardized attributes. (defconst vhdl-08-attributes '("instance_name" "path_name") (#$ . 191669))#@43 List of VHDL-AMS standardized attributes. (defconst vhdl-ams-attributes '("across" "through" "reference" "contribution" "tolerance" "dot" "integ" "delayed" "above" "zoh" "ltf" "ztf" "ramp" "slew") (#$ . 191790))#@50 List of VHDL'02 standardized enumeration values. (defconst vhdl-02-enum-values '("true" "false" "note" "warning" "error" "failure" "read_mode" "write_mode" "append_mode" "open_ok" "status_error" "name_error" "mode_error" "fs" "ps" "ns" "us" "ms" "sec" "min" "hr" "right" "left") (#$ . 192007))#@51 List of VHDL-AMS standardized enumeration values. (defconst vhdl-ams-enum-values '("quiescent_domain" "time_domain" "frequency_domain" "eps0" "mu0" "ground" "mecvf_gnd" "mecpf_gnd" "rot_gnd" "fld_gnd") (#$ . 192306))#@42 List of VHDL-AMS standardized constants. (defconst vhdl-ams-constants '("phys_q" "phys_eps0" "phys_mu0" "phys_k" "phys_gravity" "phys_ctok" "phys_c" "phys_h" "phys_h_over_2_pi" "yocto" "zepto" "atto" "femto" "pico" "nano" "micro" "milli" "centi" "deci" "deka" "hecto" "kilo" "mega" "giga" "tera" "peta" "exa" "zetta" "yotta" "deca" "phys_eps_si" "phys_eps_sio2" "phys_e_si" "phys_e_sio2" "phys_e_poly" "phys_nu_si" "phys_nu_poly" "phys_rho_poly" "phys_rho_sio2" "ambient_temperature" "ambient_pressure" "ambient_illuminance") (#$ . 192528))#@47 List of Math Packages standardized constants. (defconst vhdl-math-constants '("math_1_over_e" "math_1_over_pi" "math_1_over_sqrt_2" "math_2_pi" "math_3_pi_over_2" "math_cbase_1" "math_cbase_j" "math_czero" "math_deg_to_rad" "math_e" "math_log10_of_e" "math_log2_of_e" "math_log_of_10" "math_log_of_2" "math_pi" "math_pi_over_2" "math_pi_over_3" "math_pi_over_4" "math_rad_to_deg" "math_sqrt_2" "math_sqrt_pi") (#$ . 193074))#@41 List of VHDL'02 standardized functions. (defconst vhdl-02-functions '("now" "resolved" "rising_edge" "falling_edge" "read" "readline" "hread" "oread" "write" "writeline" "hwrite" "owrite" "endfile" "resize" "is_X" "std_match" "shift_left" "shift_right" "rotate_left" "rotate_right" "to_unsigned" "to_signed" "to_integer" "to_stdLogicVector" "to_stdULogic" "to_stdULogicVector" "to_bit" "to_bitVector" "to_X01" "to_X01Z" "to_UX01" "to_01" "conv_unsigned" "conv_signed" "conv_integer" "conv_std_logic_vector" "shl" "shr" "ext" "sxt" "deallocate") (#$ . 193504))#@41 List of VHDL'08 standardized functions. (defconst vhdl-08-functions '("finish" "flush" "justify" "maximum" "minimum" "resolution_limit" "rising_edge" "stop" "swrite" "tee" "to_binarystring" "to_bstring" "to_hexstring" "to_hstring" "to_octalstring" "to_ostring" "to_string") (#$ . 194069))#@42 List of VHDL-AMS standardized functions. (defconst vhdl-ams-functions '("frequency") (#$ . 194363))#@47 List of Math Packages standardized functions. (defconst vhdl-math-functions '("arccos" "arccosh" "arcsin" "arcsinh" "arctan" "arctanh" "arg" "cbrt" "ceil" "cmplx" "complex_to_polar" "conj" "cos" "cosh" "exp" "floor" "get_principal_value" "log" "log10" "log2" "polar_to_complex" "realmax" "realmin" "round" "sign" "sin" "sinh" "sqrt" "tan" "tanh" "trunc" "uniform") (#$ . 194468))#@54 List of VHDL'02 standardized packages and libraries. (defconst vhdl-02-packages '("std_logic_1164" "numeric_std" "numeric_bit" "standard" "textio" "std_logic_arith" "std_logic_signed" "std_logic_unsigned" "std_logic_misc" "std_logic_textio" "ieee" "std" "work") (#$ . 194853))#@54 List of VHDL'08 standardized packages and libraries. (defconst vhdl-08-packages '("env" "numeric_std_signed" "numeric_std_unsigned" "ieee_bit_context" "ieee_std_context") (#$ . 195135))#@55 List of VHDL-AMS standardized packages and libraries. (defconst vhdl-ams-packages '("fundamental_constants" "material_constants" "energy_systems" "electrical_systems" "mechanical_systems" "radiant_systems" "thermal_systems" "fluidic_systems") (#$ . 195326))#@60 List of Math Packages standardized packages and libraries. (defconst vhdl-math-packages '("math_real" "math_complex") (#$ . 195589))#@47 List of VHDL'08 standardized tool directives. (defconst vhdl-08-directives '("author" "author_info" "begin" "begin_protected" "comment" "data_block" "data_keyname" "data_keyowner" "data_method" "decrypt_license" "digest_block" "digest_key_method" "digest_keyname" "digest_keyowner" "digest_method" "encoding" "encrypt_agent" "encrypt_agent_info" "end" "end_protected" "key_block" "key_keyname" "key_keyowner" "key_method" "runtime_license" "viewport") (#$ . 195727))#@24 List of VHDL keywords. (defvar vhdl-keywords nil (#$ . 196199))#@34 List of VHDL standardized types. (defvar vhdl-types nil (#$ . 196268))#@39 List of VHDL standardized attributes. (defvar vhdl-attributes nil (#$ . 196344))#@47 List of VHDL standardized enumeration values. (defvar vhdl-enum-values nil (#$ . 196430))#@38 List of VHDL standardized constants. (defvar vhdl-constants nil (#$ . 196525))#@38 List of VHDL standardized functions. (defvar vhdl-functions nil (#$ . 196609))#@51 List of VHDL standardized packages and libraries. (defvar vhdl-packages nil (#$ . 196693))#@51 List of VHDL standardized packages and libraries. (defvar vhdl-directives nil (#$ . 196789))#@36 List of additional reserved words. (defvar vhdl-reserved-words nil (#$ . 196887))#@27 Regexp for VHDL keywords. (defvar vhdl-keywords-regexp nil (#$ . 196974))#@37 Regexp for VHDL standardized types. (defvar vhdl-types-regexp nil (#$ . 197053))#@42 Regexp for VHDL standardized attributes. (defvar vhdl-attributes-regexp nil (#$ . 197139))#@50 Regexp for VHDL standardized enumeration values. (defvar vhdl-enum-values-regexp nil (#$ . 197235))#@41 Regexp for VHDL standardized constants. (defvar vhdl-constants-regexp nil (#$ . 197340))#@41 Regexp for VHDL standardized functions. (defvar vhdl-functions-regexp nil (#$ . 197434))#@54 Regexp for VHDL standardized packages and libraries. (defvar vhdl-packages-regexp nil (#$ . 197528))#@39 Regexp for additional reserved words. (defvar vhdl-reserved-words-regexp nil (#$ . 197634))#@70 Upcase all elements in LIST based on CONDITION. (fn CONDITION LIST) (defalias 'vhdl-upcase-list #[514 "\203�\211\211\203�\211@\226\240\210\211A\262\202�\210\207" [] 5 (#$ . 197731)])#@28 Initialize reserved words. (defalias 'vhdl-words-init #[0 "\306\205� \307\n\310\311!\205� \310\312!\205�\f#\"\306\205 �\307\310\311!\205+�\310\312!\2053�\310\313!\205;�$\"\306\205F�\307\310\311!\205Q�\310\312!\205Y�#\"\306\205d�\307 \310\312!\205o�!\"\"\"\306\205z�#\307\310\312!\205\203�$\310\313!\205\213�%\314#\"&\307'\310\311!\205\233�(\310\312!\205\243�)\310\313!\205\253�*$+\307,\310\311!\205\271�-\310\312!\205\301�.\310\313!\205\311�/$0\310\311!\205\324�12\3073\205\336�45\205\345�6\315#7\316\317 !\320Q8\316\317!\320Q9\316\317!\320Q:\316\317\"!\320Q;\316\317&!\320Q<\316\317+!\320Q=\316\3170!\320Q>\316?\321\232?\2054?\322P\3177!\320R@\323 \207" [vhdl-highlight-case-sensitive vhdl-upper-case-keywords vhdl-02-keywords vhdl-08-keywords vhdl-ams-keywords vhdl-keywords vhdl-upcase-list append vhdl-standard-p 8 ams math (#1="") (#1#) "\\<\\(" regexp-opt "\\)\\>" #1# "\\|" vhdl-abbrev-list-init vhdl-upper-case-types vhdl-02-types vhdl-08-types vhdl-ams-types vhdl-math-types vhdl-types vhdl-upper-case-attributes vhdl-02-attributes vhdl-08-attributes vhdl-ams-attributes vhdl-attributes vhdl-upper-case-enum-values vhdl-02-enum-values vhdl-ams-enum-values vhdl-enum-values vhdl-upper-case-constants vhdl-ams-constants vhdl-math-constants vhdl-constants vhdl-02-functions vhdl-08-functions vhdl-ams-functions vhdl-math-functions vhdl-functions vhdl-02-packages vhdl-08-packages vhdl-ams-packages vhdl-math-packages vhdl-packages vhdl-08-directives vhdl-directives vhdl-highlight-forbidden-words vhdl-forbidden-words vhdl-highlight-verilog-keywords vhdl-verilog-keywords vhdl-reserved-words vhdl-keywords-regexp vhdl-types-regexp vhdl-attributes-regexp vhdl-enum-values-regexp vhdl-constants-regexp vhdl-functions-regexp vhdl-packages-regexp vhdl-forbidden-syntax vhdl-reserved-words-regexp] 8 (#$ . 197926)])#@36 Predefined abbreviations for VHDL. (defvar vhdl-abbrev-list nil (#$ . 199825)) (defalias 'vhdl-abbrev-list-init #[0 "\306C \nC \fC \nC \fC \307\310\311&\211\207" [vhdl-upper-case-keywords vhdl-keywords vhdl-upper-case-types vhdl-types vhdl-upper-case-attributes vhdl-attributes append (nil) (nil) (nil) vhdl-upper-case-enum-values vhdl-enum-values vhdl-upper-case-constants vhdl-constants vhdl-functions vhdl-packages vhdl-directives vhdl-abbrev-list] 17]) (vhdl-words-init)#@210 Regexp describing a VHDL symbol. We cannot use just `word' syntax class since `_' cannot be in word class. Putting underscore in word class breaks forward word movement behavior that users are familiar with. (defconst vhdl-symbol-key "\\(\\w\\|\\s_\\)+" (#$ . 200320))#@48 Regexp describing a case statement header key. (defconst vhdl-case-header-key "case[( \n \f][^;=>]+[) \n \f]is" (#$ . 200595))#@33 Regexp describing a VHDL label. (defconst vhdl-label-key (concat "\\(" vhdl-symbol-key "\\s-*:\\)[^=]") (#$ . 200729))#@446 Return the value of point at certain commonly referenced POSITIONs. POSITION can be one of the following symbols: bol -- beginning of line eol -- end of line bod -- beginning of defun boi -- back to indentation eoi -- last whitespace on line ionl -- indentation of next line iopl -- indentation of previous line bonl -- beginning of next line bopl -- beginning of previous line This function does not modify point or mark. (fn POSITION) (defalias 'vhdl-point '(macro . #[257 "\211\242\300=\203 �\211AA\203�\301\302\"\210\211A@\262\303\304\305\306\267\202D�\307\202H�\310\202H�\311\202H�\312\202H�\313\202H�\314\202H�\315\202H�\316\202H�\317\202H�\301\320\"\321\322#BB\207" [quote error "ERROR: Bad buffer position requested: %s" let ((here (point))) append #s(hash-table size 9 test eq rehash-size 1.5 rehash-threshold 0.8125 purecopy t data (bol 32 eol 36 bod 40 boi 44 eoi 48 bonl 52 bopl 56 iopl 60 ionl 64)) ((beginning-of-line)) ((end-of-line)) ((save-match-data (vhdl-beginning-of-defun))) ((back-to-indentation)) ((end-of-line) (skip-chars-backward " ")) ((forward-line 1)) ((forward-line -1)) ((forward-line -1) (back-to-indentation)) ((forward-line 1) (back-to-indentation)) "ERROR: Unknown buffer position requested: %s" ((prog1 (point) (goto-char here))) nil] 7 (#$ . 200854)]))#@72 Safely execute BODY, return nil if an error occurred. (fn &rest BODY) (defalias 'vhdl-safe '(macro . #[128 "\300\301\302B\303BBB\207" [condition-case nil progn ((error nil))] 5 (#$ . 202165)]))#@146 A simple macro to append the syntax in SYMBOL to the syntax list. Try to increase performance by using this macro. (fn SYMBOL &optional RELPOS) (defalias 'vhdl-add-syntax '(macro . #[513 "\300\301\302\211E\303BBE\207" [setq vhdl-syntactic-context cons (vhdl-syntactic-context)] 8 (#$ . 202367)]))#@111 A simple macro to return check the syntax list. Try to increase performance by using this macro. (fn SYMBOL) (defalias 'vhdl-has-syntax '(macro . #[257 "\300\301BB\207" [assoc (vhdl-syntactic-context)] 4 (#$ . 202673)]))#@95 Read new offset value for LANGELEM from minibuffer. Return a valid value only. (fn LANGELEM) (defalias 'vhdl-read-offset #[257 "\301\302\236\243\"\303\304\211\211\204p�\305\"\262\306\230\203 �\307\202k�\310\230\203*�\311\202k�\312\230\2034�\313\202k�\314\230\203>�\315\202k�\316\317\"\203K�\320!\202k�\321\322!\211\262!\203Z�\211\202k�\323!\203d�\211\202k�\324 \210\325\262\304\262\202 �\207" [vhdl-offsets-alist format "%s" "Offset: " nil read-string "+" + "-" - "++" ++ "--" -- string-match "^-?[0-9]+$" string-to-number fboundp intern boundp ding "Offset must be int, func, var, or one of +, -, ++, --: "] 9 (#$ . 202901)])#@310 Change the value of a syntactic element symbol in `vhdl-offsets-alist'. SYMBOL is the syntactic element symbol to change and OFFSET is the new offset for that syntactic element. Optional ADD-P says to add SYMBOL to `vhdl-offsets-alist' if it doesn't already appear there. (fn SYMBOL OFFSET &optional ADD-P) (defalias 'vhdl-set-offset #[770 "\301=\204.�\302=\204.�\303=\204.�\304=\204.�\250\204.�\305!\204.�\306!\204.�\307\310\"\210\236\211\203=�\211\241\266\202Q�\203K�BB\210\202Q�\307\311\"\266\312 \207" [vhdl-offsets-alist + - ++ -- fboundp boundp error "ERROR: Offset must be int, func, var, or one of +, -, ++, --: %s" "ERROR: %s is not a valid syntactic symbol" vhdl-keep-region-active] 7 (#$ . 203554) (byte-code "\302\303\304\203 �\305\202\f�\306\307Q\310\311 \"\312?\313 \211G\314\315S8@\"\266\202%!\316!E\207" [current-prefix-arg vhdl-offsets-alist intern completing-read "Syntactic symbol to change" " or add" "" ": " mapcar #[257 "\300\301@\"C\207" [format "%s"] 4 "\n\n(fn LANGELEM)"] nil vhdl-get-syntactic-context format "%s" vhdl-read-offset] 12)])#@446 Set `vhdl-mode' variables to use one of several different indentation styles. STYLE is a string representing the desired style and optional LOCAL is a flag which, if non-nil, means to make the style variables being changed buffer local, instead of the default, which is to set the global variables. Interactively, the flag comes from the prefix argument. The styles are chosen from the `vhdl-style-alist' variable. (fn STYLE &optional LOCAL) (defalias 'vhdl-set-style #[513 "\301\"A\211\204�\302\303\"\210\304\305\306\"\"\266\307 \207" [vhdl-style-alist assoc error "ERROR: Invalid VHDL indentation style `%s'" mapc make-closure #[257 "\211@A\302=\204�\300\203�\303!\202�L\207\300\203\"�\303!\202#�\304 !L\210\305\306\"\207" [V0 vhdl-offsets-alist-default vhdl-offsets-alist make-local-variable copy-alist mapcar #[257 "\211@A\300\"\207" [vhdl-set-offset] 6 "\n\n(fn LANGENTRY)"]] 6 "\n\n(fn VARENTRY)"] vhdl-keep-region-active] 7 (#$ . 204657) (byte-code "\302\303\304\305$ D\207" [vhdl-style-alist current-prefix-arg completing-read "Use which VHDL indentation style? " nil t] 5)])#@285 Get offset from LANGELEM which is a cons cell of the form: (SYMBOL . RELPOS). The symbol is matched against vhdl-offsets-alist and the offset found there is either returned, or added to the indentation at RELPOS. If RELPOS is nil, then the offset is simply returned. (fn LANGELEM) (defalias 'vhdl-get-offset #[257 "\211@A\236\211\243\204\"� \203�\303\304\"\210\202c�\305\262\305\262\202c�\211\306\267\202F�\n\262\202c�\n[\262\202c�\307\n_\262\202c�\307\n[_\262\202c�\211\247\204Y�\310!\203Y�\211!\262\202c�\211\247\204c�\311!\262\203�`\312 \210`b\210\262W\203�\212b\210i)\202\200�\305\\\207" [vhdl-offsets-alist vhdl-strict-syntax-p vhdl-basic-offset error "ERROR: Don't know how to indent a %s" 0 #s(hash-table size 4 test eq rehash-size 1.5 rehash-threshold 0.8125 purecopy t data (+ 40 - 46 ++ 53 -- 61)) 2 fboundp eval beginning-of-line] 9 (#$ . 205773)])#@83 Check if point is in a comment (include multi-line comments). (fn &optional POS) (defalias 'vhdl-in-comment-p #[256 "\300\212\206�`b\210\211`!\206�\301 \210l?\205�\302u\210\211`!)\207" [#[257 "\211f\211\203 �\211z\300=\206�\301\302\212\303 \210`)\"8\207" [60 4 parse-partial-sexp beginning-of-defun] 6 "\n\n(fn P)"] back-to-indentation nil] 4 (#$ . 206667)])#@32 Check if point is in a string. (defalias 'vhdl-in-string-p #[0 "\300 \301=\207" [vhdl-in-literal string] 2 (#$ . 207038)])#@37 Check if point is in a quote ('x'). (defalias 'vhdl-in-quote-p #[0 "`eV\203!�`TdW\203!�`\206�`Sf\300U\203!�`Tf\300U\206?�`SeV\205?�`dW\205?�`S\2064�`Sf\300U\205?�`f\300U\207" [39] 2 (#$ . 207166)])#@42 Determine if point is in a VHDL literal. (defalias 'vhdl-in-literal #[0 "\212\300`\301 \210`b\210\262`\"\3028\203�\303\202D�\3048\203\"�\305\202D�\306 \203+�\307\202D�\310 \2034�\311\202D�\312\313!\203C�\314 \203C�\305\202D�\315)\207" [parse-partial-sexp beginning-of-line 3 string 4 comment vhdl-beginning-of-macro pound vhdl-beginning-of-directive directive vhdl-standard-p 8 vhdl-in-comment-p nil] 4 (#$ . 207370)])#@70 Determine if point is inside extended identifier (delimited by `\'). (defalias 'vhdl-in-extended-identifier-p #[0 "\300 \301\302\"\216\212\303\304`\305 \210`b\210\262\306#)\205*�\212\307\304`\310\210`b\210\262\306#))\207" [match-data make-closure #[0 "\301\300\302\"\207" [V0 set-match-data t] 3] re-search-backward "\\\\" beginning-of-line t re-search-forward nil] 6 (#$ . 207799)])#@134 Skip all comments (including whitespace). Skip backwards if DIRECTION is negative, skip forward otherwise. (fn &optional DIRECTION) (defalias 'vhdl-forward-comment #[256 "\211\203*�\211\300W\203*�\301\302x\210\303\304`\305 \210`b\210\262\306#\205?�\307\224b\210\301\302x\210\202�\301\302w\210\310\311!\205?�\300\225b\210\301\302w\210\202.�\207" [0 " \n \f" nil re-search-backward "^[^\"-]*\\(\\(-?\"[^\"]*\"\\|-[^\"-]\\)[^\"-]*\\)*\\(--\\)" beginning-of-line t 3 looking-at "--.*"] 6 (#$ . 208195) "p"]) (defalias 'vhdl-forward-comment 'forward-comment)#@64 Move point to the first non-whitespace character on this line. (defalias 'vhdl-back-to-indentation #[0 "\300\301!\210\302\303`\304\210`b\210\262\"\207" [beginning-of-line 1 skip-syntax-forward " " nil] 5 (#$ . 208759) nil])#@62 Determine if point is in a VHDL literal. (fn &optional LIM) (defalias 'vhdl-win-il #[256 "\212`\300\211\206�`\301 \302\303\"\216\304 )\266`b\210\262\211b\210`W\203\231�\305\306\307#\2051�\310\224\310\225{\262\204;�\300\202\224�\311\230\203N�\300\210`X\205\224�\312\202\224�\313\230\203a�\300\210`X\205\224�\314\202\224�\315\230\203z�\214`}\210\305\316\307#)?\205\224�\317\202\224�\320\230\203\223�\214`}\210\305\321\307#)?\205\224�\317\202\224�\300\262\202�\266\204)\207" [nil match-data make-closure #[0 "\301\300\302\"\207" [V0 set-match-data t] 3] vhdl-beginning-of-defun re-search-forward "--\\|[\"']\\|`" move 0 "--" comment "`" directive "\"" "\\([^\\]\\|^\\)\\(\\\\\\\\\\)*\"" string "'" "\\([^\\]\\|^\\)\\(\\\\\\\\\\)?'"] 9 (#$ . 208991)]) (byte-code "\301\302\"\203 �\303\304M\210\301\207" [emacs-version string-match "Win-Emacs" vhdl-in-literal vhdl-win-il] 3)#@59 Forward skip of syntactic whitespace. (fn &optional LIM) (defalias 'vhdl-forward-syntactic-ws #[256 "dd`U\204N�`\262\300!\210\301f\302=\204�\301f\303=\203�`\304 \210`b\210\262`U\203�`\301\210`b\210\262\206:�`Sf\305=\203H�\306y\307U\204,�\301\210\202�\205V�`^b\207" [vhdl-forward-comment nil 35 96 back-to-indentation 92 1 0] 6 (#$ . 209894)])#@70 Forward skip syntactic whitespace for Win-Emacs. (fn &optional LIM) (defalias 'vhdl-win-fsws #[256 "\211\206�d\300\211?\205!�\301w\210\302\303!\203�\300\210\202�\304\262\202�\207" [nil " \n \f" looking-at "--" t] 5 (#$ . 210258)]) (byte-code "\301\302\"\203 �\303\304M\210\301\207" [emacs-version string-match "Win-Emacs" vhdl-forward-syntactic-ws vhdl-win-fsws] 3)#@94 Go to the beginning of a cpp macro definition (nicked from `cc-engine'). (fn &optional LIM) (defalias 'vhdl-beginning-of-macro #[256 "`\300 \210`S\206\n�`Sf\301=\203�\302y\210\202�\303 \210`X\203)�\304f\305=\203)�\306\207\211b\210\304\207" [beginning-of-line 92 -1 back-to-indentation nil 35 t] 4 (#$ . 210639)])#@83 Go to the beginning of a directive (nicked from `cc-engine'). (fn &optional LIM) (defalias 'vhdl-beginning-of-directive #[256 "`\300 \210`S\206\n�`Sf\301=\203�\302y\210\202�\303 \210`X\203)�\304f\305=\203)�\306\207\211b\210\304\207" [beginning-of-line 92 -1 back-to-indentation nil 96 t] 4 (#$ . 210961)])#@62 Backward skip over syntactic whitespace. (fn &optional LIM) (defalias 'vhdl-backward-syntactic-ws #[256 "ed[`U\204�`\262\300!\210\301 \210\202�\205�`]b\207" [vhdl-forward-comment vhdl-beginning-of-macro] 5 (#$ . 211276)])#@71 Backward skip syntactic whitespace for Win-Emacs. (fn &optional LIM) (defalias 'vhdl-win-bsws #[256 "\211\206�`\300 \301\302\"\216\303 )\266`b\210\262\304\211?\205U�\305x\210\306 \307=\203O�\310x\210\311x\210g\312U\203>�`Tf\312U\204�`X\204�\310x\210\311x\210\2020�\313\262\202�\207" [match-data make-closure #[0 "\301\300\302\"\207" [V0 set-match-data t] 3] vhdl-beginning-of-defun nil " \n \f" vhdl-in-literal comment "^-" "-" 45 t] 6 (#$ . 211512)]) (byte-code "\301\302\"\203 �\303\304M\210\301\207" [emacs-version string-match "Win-Emacs" vhdl-backward-syntactic-ws vhdl-win-bsws] 3)#@109 If the keyword at POINT is at boi, return (current-column) at that point. Otherwise return nil. (fn POINT) (defalias 'vhdl-first-word #[257 "\212\211b\205�``\300 \210`b\210\262=\205�i)\207" [back-to-indentation] 5 (#$ . 212124)])#@111 If keyword at POINT is at eoi, then return (current-column) at that point. Otherwise, return nil. (fn POINT) (defalias 'vhdl-last-word #[257 "\212\211b\205%�\212\300 \210``\301\210\302\301x\210`b\210\262=\206 �\303\304!)\205%�i)\207" [forward-sexp nil " " looking-at "\\s-*\\(--\\)?"] 5 (#$ . 212365)]) (defconst vhdl-libunit-re "\\b\\(architecture\\|configuration\\|context\\|entity\\|package\\)\\b[^_]") (defalias 'vhdl-libunit-p #[0 "\212\300 \210\301\302w\210\303\304!)?\205&�\212\305 \210\303\306!?\205%�\300 \210\307 \210g\310U?)\207" [forward-sexp " \n \f" nil looking-at "is\\b[^_]" backward-sexp "use\\b[^_]" vhdl-forward-syntactic-ws 58] 2]) (defconst vhdl-defun-re "\\b\\(architecture\\|block\\|configuration\\|context\\|entity\\|package\\|process\\|procedural\\|procedure\\|function\\)\\b[^_]") (defalias 'vhdl-defun-p #[0 "\212\300\301!\203�\212\302 \210\300\303!)?\202�\304)\207" [looking-at "block\\|process\\|procedural" backward-sexp "end\\s-+\\w" t] 2])#@169 If the word at the current position corresponds to a "defun" keyword, then return a string that can be used to find the corresponding "begin" keyword, else return nil. (defalias 'vhdl-corresponding-defun #[0 "\212\301!\205�\302 \205�\301\303!\203�\304\224\304\225{\202�\305)\207" [vhdl-defun-re looking-at vhdl-defun-p "block\\|process\\|procedural" 0 "is"] 2 (#$ . 213351)])#@71 Regexp for searching forward that matches all known "begin" keywords. (defconst vhdl-begin-fwd-re "\\b\\(is\\|begin\\|block\\|component\\|generate\\|then\\|else\\|loop\\|process\\|procedural\\(\\s-+body\\)?\\|units\\|use\\|record\\|protected\\(\\s-+body\\)?\\|for\\)\\b\\([^_]\\|\\'\\)" (#$ . 213737))#@72 Regexp for searching backward that matches all known "begin" keywords. (defconst vhdl-begin-bwd-re "\\b\\(is\\|begin\\|block\\|component\\|generate\\|then\\|else\\|loop\\|process\\|procedural\\(\\s-+body\\)?\\|units\\|use\\|record\\|protected\\(\\s-+body\\)?\\|for\\)\\b[^_]" (#$ . 214044))#@285 Return t if we are looking at a real "begin" keyword. Assumes that the caller will make sure that we are looking at vhdl-begin-fwd-re, and are not inside a literal, and that we are not in the middle of an identifier that just happens to contain a "begin" keyword. (fn &optional LIM) (defalias 'vhdl-begin-p #[256 "\301\302!\203D�\212\303 \210\304\305w\210\305\211\2042�\306\307\310#\2032�h\311U\204&�\312 \203,�\313u\210\202�\314\262\202�\210g\315U?\205>�\301\316!?)\203D�\314\207\301\317!\203L�\314\207\301\320!\203h�\212\321\322\310#\210g\315=\206b�`=)\203h�\314\207\301\323!\203{�\212\303 \210\301\324!)\204{�\314\207\301\325!\203\232�\212\303 \210\301\324!)\204\232�\212\326!\210h\327U)\204\232�\314\207\301\330!\205\263�\212\303 \210\301\324!)?\205\263�\331\236\205\263�\314\207" [vhdl-syntactic-context looking-at "i" backward-sexp "(" nil re-search-backward ";\\|\\b\\(architecture\\|case\\|configuration\\|context\\|entity\\|package\\|procedure\\|return\\|is\\|begin\\|process\\|procedural\\|block\\)\\b[^_]" move 95 vhdl-in-literal -1 t 59 "is\\|begin\\|process\\|procedural\\|block" "be\\|t\\|use" "e" vhdl-re-search-backward ";\\|\\bwhen\\b[^_]" "block\\|generate\\|loop\\|process\\|procedural\\|protected\\(\\s-+body\\)?\\|units\\|record" "end\\s-+\\w" "c" vhdl-backward-syntactic-ws 58 "f" configuration] 6 (#$ . 214341)])#@22 (fn &optional LIM) (defalias 'vhdl-corresponding-mid #[256 "\300\301!\203�\302\207\300\303!\203�\304\207\305\207" [looking-at "is\\|block\\|generate\\|process\\|procedural" "begin" "then\\|use" "<else>" "end"] 3 (#$ . 215691)])#@469 If the word at the current position corresponds to a "begin" keyword, then return a vector containing enough information to find the corresponding "end" keyword, else return nil. The keyword to search forward for is aref 0. The column in which the keyword must appear is aref 1 or nil if any column is suitable. Assumes that the caller will make sure that we are not in the middle of an identifier that just happens to contain a "begin" keyword. (fn &optional LIM) (defalias 'vhdl-corresponding-end #[256 "\212\301!\205\303�\301\302!\203�\212\303 \210\301\304!)\205\303�h\305U?\205\303�\306 ?\205\303�\307!\205\303�\301\310!\203P�\311\312\313`!\205L�\314`!\206L�\212\315!\210\316!\210\314`!)\"\202\303�\301\317!\203u�\311\312\313`!\205q�\314`!\206q�\212\315!\210\316!\210\314`!)\"\202\303�\301\320!\203\202�\311\312\321\"\202\303�\301\322!\203\241�\311\312\314`!\206\235�\212\315!\210\316!\210\314`!)\"\202\303�\301\323!\205\303�\311\324\313`!\205\302�\314`!\206\302�\212\315!\210\316!\210\314`!)\")\207" [vhdl-begin-fwd-re looking-at "\\<use\\>" back-to-indentation "\\(\\w+\\s-*:\\s-*\\)?\\<\\(case\\|elsif\\|if\\)\\>" 95 vhdl-in-literal vhdl-begin-p "[igl]" vector "end" vhdl-last-word vhdl-first-word vhdl-beginning-of-statement-1 vhdl-backward-skip-label "be\\|[ef]" "component\\|units\\|protected\\(\\s-+body\\)?\\|record" nil "bl\\|p" "t\\|use" "elsif\\|else\\|end\\s-+\\(if\\|use\\)"] 5 (#$ . 215929)]) (defconst vhdl-end-fwd-re "\\b\\(end\\|else\\|elsif\\)\\b\\([^_]\\|\\'\\)") (defconst vhdl-end-bwd-re "\\b\\(end\\|else\\|elsif\\)\\b[^_]")#@280 Return t if we are looking at a real "end" keyword. Assumes that the caller will make sure that we are looking at vhdl-end-fwd-re, and are not inside a literal, and that we are not in the middle of an identifier that just happens to contain an "end" keyword. (fn &optional LIM) (defalias 'vhdl-end-p #[256 "\300\301!?\206�\212\302\303\304#\210g\305=\206�`=\206�\306 )\207" [looking-at "else" re-search-backward ";\\|\\bwhen\\b[^_]" move 59 vhdl-in-literal] 5 (#$ . 217500)])#@646 If the word at the current position corresponds to an "end" keyword, then return a vector containing enough information to find the corresponding "begin" keyword, else return nil. The keyword to search backward for is aref 0. The column in which the keyword must appear is aref 1 or nil if any column is suitable. The supplementary keyword to search forward for is aref 2 or nil if this is not required. If aref 3 is t, then the "begin" keyword may be found in the middle of a statement. Assumes that the caller will make sure that we are not in the middle of an identifier that just happens to contain an "end" keyword. (fn &optional LIM) (defalias 'vhdl-corresponding-begin #[256 "\212\301\302!\205\307�\303 ?\205\307�\304!\205\307�\302\305!\203%�\306\307\310`!\311\301$\202\307�`\262\312 \210\313\301w\210\302\314!\203@�\306\315\310!\316\301$\202\307�\302\317!\203U�\306\320\224\320\225{\310!\301\211$\202\307�\302\321!\203j�\306\320\224\320\225{\310!\301\322$\202\307�\302\323!\203{�\306\324\310!\301\211$\202\307�\302\325!\203\214�\306\326\310!\327\301$\202\307�\302\330!\203\235�\306\331\310!\332\301$\202\307�\302\333!\203\256�\306\334\310!\335\301$\202\307�\302\336!\203\277�\306\337\310!\301\211$\202\307�\306\340\310!\341\301$)\207" [vhdl-end-fwd-re nil looking-at vhdl-in-literal vhdl-end-p "el" vector "if\\|elsif" vhdl-first-word "then\\|use" forward-sexp " \n \f" "if\\b[^_]" "else\\|elsif\\|if" "else\\|then\\|use" "component\\b[^_]" 1 "\\(units\\|record\\|protected\\(\\s-+body\\)?\\)\\b[^_]" t "\\(block\\|process\\|procedural\\)\\b[^_]" "begin" "case\\b[^_]" "case" "is" "generate\\b[^_]" "generate\\|for\\|if" "generate" "loop\\b[^_]" "loop\\|while\\|for" "loop" "for\\b[^_]" "for" "begin\\|architecture\\|configuration\\|context\\|entity\\|package\\|procedure\\|function" (("begin") ("architecture" . "is") ("configuration" . "is") ("context" . "is") ("entity" . "is") ("package" . "is") ("procedure" . "is") ("function" . "is"))] 7 (#$ . 217987)]) (defconst vhdl-leader-re "\\b\\(block\\|component\\|process\\|procedural\\|for\\)\\b[^_]") (defalias 'vhdl-end-of-leader #[0 "\212\300\301!\203.�\212\302 \210\303\304w\210g\305U)\203�\302\306!\210\202 �\302 \210\300\307!\203*�\310\225b\210`\202i�\300\311!\203F�\302\306!\210\300\307!\203B�\310\225b\210`\202i�\300\312!\203h�\302\306!\210\303\304w\210\300\313!\203d�\302 \210\303\304w\210\202T�`\202i�\304)\207" [looking-at "block\\|process\\|procedural" forward-sexp " \n \f" nil 40 2 "[ \n \f]*is" 0 "component" "for" "[,:(]"] 2]) (defconst vhdl-trailer-re "\\b\\(is\\|then\\|generate\\|loop\\|record\\|protected\\(\\s-+body\\)?\\|use\\)\\b[^_]")#@75 Regexp for searching forward that matches all known "statement" keywords. (defconst vhdl-statement-fwd-re "\\b\\(if\\|for\\|while\\|loop\\)\\b\\([^_]\\|\\'\\)" (#$ . 220630))#@76 Regexp for searching backward that matches all known "statement" keywords. (defconst vhdl-statement-bwd-re "\\b\\(if\\|for\\|while\\|loop\\)\\b[^_]" (#$ . 220810))#@297 Return t if we are looking at a real "statement" keyword. Assumes that the caller will make sure that we are looking at vhdl-statement-fwd-re, and are not inside a literal, and that we are not in the middle of an identifier that just happens to contain a "statement" keyword. (fn &optional LIM) (defalias 'vhdl-statement-p #[256 "\300\301!\203#�\212\302\303!\210\304\305w\210\300\306!)\203#�\212\307 \210\300\310!)\204#�\311\207\300\312!\2036�\212\307 \210\300\310!)\2046�\311\207\300\313!\205=�\311\207" [looking-at "f" forward-sexp 2 " \n \f" nil "in\\b[^_]" backward-sexp "end\\s-+\\w" t "i" "w"] 3 (#$ . 220980)])#@53 Regexp describing a case statement alternative key. (defconst vhdl-case-alternative-re "when[( \n \f][^;=>]+=>" (#$ . 221605))#@292 Return t if we are looking at a real case alternative. Assumes that the caller will make sure that we are looking at vhdl-case-alternative-re, and are not inside a literal, and that we are not in the middle of an identifier that just happens to contain a "when" keyword. (fn &optional LIM) (defalias 'vhdl-case-alternative-p #[256 "\212\300\211\204%�\301\302\303#\203%�h\304U\204�\305 \203�\306u\210\202�\307\262\202�g\310=\206.�`=)\207" [nil re-search-backward ";\\|<=" move 95 vhdl-in-literal -1 t 59] 6 (#$ . 221739)]) (defconst vhdl-b-t-b-re (concat vhdl-begin-bwd-re "\\|" vhdl-end-bwd-re))#@77 Move backward to the previous "begin" or "end" keyword. (fn &optional LIM) (defalias 'vhdl-backward-to-block #[256 "\303\211\204_�\304\305#\203_�h\306U\204�\307 \203�\310u\210\202�\311 !\203G�\311\312!\2035�\212\313 \210\311\314!)\203G�h\306U\204G�\315!\203G�\316\262\202�\311\n!\203�h\306U\204�\317!\203�\320\262\202�\207" [vhdl-b-t-b-re vhdl-begin-fwd-re vhdl-end-fwd-re nil re-search-backward move 95 vhdl-in-literal -1 looking-at "\\<use\\>" back-to-indentation "\\(\\w+\\s-*:\\s-*\\)?\\<\\(case\\|elsif\\|if\\)\\>" vhdl-begin-p begin vhdl-end-p end] 6 (#$ . 222348)])#@114 Move forward across one balanced expression (sexp). With COUNT, do it that many times. (fn &optional COUNT LIM) (defalias 'vhdl-forward-sexp #[512 "\206�\302\303\304\211\212\305V\203\307�\306\304w\210\307 !\2036�h\310U\2046�\311 \2046�\312!\2036�\307\313!\2046�\314\315!\210\316!\211\262\203\275�\317\305H\320Q\302H`\304\210`b\210\262\304\211\211\204\260�\321\304\303#\203\260�\302\225\211\262\203\260�\305\224b\203\260�\203\201�\322 U\204\201�`V\204\217�h\310U\204\217�\311 \211\262\203\241�\323=\203\233�\304\210\202U�\304u\210\202U�\307\313!\204\252�\211b\210\303\262\202U�\204\270�\314\324!\210\266\202\300�\325 \210S\262\202 �`)\262\211b)\210\304\207" [case-fold-search vhdl-end-fwd-re 1 t nil 0 " \n \f" looking-at 95 vhdl-in-literal vhdl-end-p "else" error "ERROR: Containing expression ends prematurely in vhdl-forward-sexp" vhdl-corresponding-end "\\b\\(" "\\)\\b\\([^_]\\|\\'\\)" re-search-forward current-indentation comment "ERROR: Unbalanced keywords in vhdl-forward-sexp" forward-sexp] 16 (#$ . 222942) "p"])#@159 Move backward across one balanced expression (sexp). With COUNT, do it that many times. LIM bounds any required backward searches. (fn &optional COUNT LIM) (defalias 'vhdl-backward-sexp #[512 "\206�\302\303\304\211\212\305V\203D\306\307!\203\"�h\310U\204\"�\311 \203Q�\312 \210\306 !\203Q�\306\313!\203<�\212\314 \210\306\315!)\203Q�h\310U\204Q�\311 \204Q�\316!\203Q�\317\320!\210\321!\211\262\203=h\310U\204=\322\305H\323Q\302H\324H`\304\211\211\2043\325 \303#\2033\302\224\302\225{\211\262\2033\203\240�\326 U\204\240�\203\253�iU\203\253�h\310U\204\253�\311 \203\261�\327u\210\202p�\330H\211\262\203-<\203\326�\331\"\262\203-A\211\262\203-\322\323Q\262\212\204\"\332\303#\203\"\302\224b\203\"h\310U\204\377�\311 \211\262\203\333=\203`\304\210`b\210\262^b\210\202\336�\304u\210\202\336�`\262\202\336�)\203p�b\210\202p�\303\262\202p�\204;\317\334!\210\266S\262\202 �`)\262\211b)\210\304\207" [case-fold-search vhdl-begin-fwd-re 1 t nil 0 looking-at "else\\b\\([^_]\\|\\'\\)" 95 vhdl-in-literal backward-sexp "\\<use\\>" back-to-indentation "\\(\\w+\\s-*:\\s-*\\)?\\<\\(case\\|elsif\\|if\\)\\>" vhdl-begin-p error "ERROR: Containing expression ends prematurely in vhdl-backward-sexp" vhdl-corresponding-begin "\\b\\(" "\\)\\b[^_]" 3 re-search-backward current-indentation -1 2 assoc re-search-forward comment "ERROR: Unbalanced keywords in vhdl-backward-sexp"] 17 (#$ . 224004) "p"])#@111 Move backward out of one level of blocks. With argument, do this that many times. (fn &optional COUNT LIMIT) (defalias 'vhdl-backward-up-list #[512 "\206�\301\302\212\303V\203\"�\304!\203�\305\306!\210\307!\210S\262\202�`)\262\211b\207" [vhdl-defun-re 1 nil 0 looking-at error "ERROR: Unbalanced blocks" vhdl-backward-to-block] 6 (#$ . 225472) "p"])#@64 Move forward to the end of a VHDL defun. (fn &optional COUNT) (defalias 'vhdl-end-of-defun #[256 "\301\302 \210\303\304!\204�\305\306!\210\307 )\207" [case-fold-search t vhdl-beginning-of-defun looking-at "block\\|process\\|procedural" re-search-forward "\\bis\\b" vhdl-forward-sexp] 3 (#$ . 225839) nil])#@54 Put mark at end of this "defun", point at beginning. (defalias 'vhdl-mark-defun #[0 "\301\302 \210\303 \210\302 \210\304\305!\204�\306\307!\210\310 \210\311 )\207" [case-fold-search t push-mark vhdl-beginning-of-defun looking-at "block\\|process\\|procedural" re-search-forward "\\bis\\b" vhdl-forward-sexp exchange-point-and-mark] 2 (#$ . 226153) nil])#@485 Move backward to the beginning of a VHDL library unit. Returns the location of the corresponding begin keyword, unless search stops due to beginning or end of buffer. Note that if point is between the "libunit" keyword and the corresponding "begin" keyword, then that libunit will not be recognized, and the search will continue backwards. If point is at the "begin" keyword, then the defun will be recognized. The returned point is at the first character of the "libunit" keyword. (defalias 'vhdl-beginning-of-libunit #[0 "`\212\301\302!\210`T)\303\211\211\204|�\304\303\305#\203|�h\306U\204(�\307 \204(�\310 \204.�\311u\210\202\f�`\262\204v�\312\313\314#\203v�\315\224\211\262\203v�h\306U\204S�\307 \211\262\203p�\316=\203j�`\303\210`b\210\262^b\210\2021�\303u\210\2021�\211\262\2021�b\210\202\f�\207" [vhdl-libunit-re forward-word-strictly 1 nil re-search-backward move 95 vhdl-in-literal vhdl-libunit-p -1 re-search-forward "\\bis\\b[^_]" t 0 comment] 9 (#$ . 226515)])#@221 Move backward to the beginning of a VHDL defun. With argument, do it that many times. Returns the location of the corresponding begin keyword, unless search stops due to beginning or end of buffer. (fn &optional COUNT) (defalias 'vhdl-beginning-of-defun #[256 "\211\206�\302\303`\304\305V\203\237�\304\262b\210\212\306\302!\210`T)\304\211\204\226�\307 \304\310#\203\226�h\311U\2047�\312 \203=�\313u\210\202 �\314 \211\262\203 �`\262\204\220�\315\303#\203\220�h\311U\204l�\316 \317\320\"\216\312 )\211\262\262\203\211�\211\321=\203\203�`\304\210`b\210\262^b\210\202H�\304u\210\202H�\305\224\262\202H�b\210\202 �\266S\262\202\n�\322 )\210\207" [case-fold-search vhdl-defun-re 1 t nil 0 forward-word-strictly re-search-backward move 95 vhdl-in-literal -1 vhdl-corresponding-defun search-forward match-data make-closure #[0 "\301\300\302\"\207" [V0 set-match-data t] 3] comment vhdl-keep-region-active] 12 (#$ . 227512) "p"])#@539 Go to the beginning of the innermost VHDL statement. With prefix arg, go back N - 1 statements. If already at the beginning of a statement then go to the beginning of the preceding one. If within a string or comment, or next to a comment (only whitespace between), move by sentences instead of statements. When called from a program, this function takes 3 optional args: the prefix arg, a buffer position limit which is the farthest back to search, and an argument indicating an interactive call. (fn &optional COUNT LIM INTERACTIVE) (defalias 'vhdl-beginning-of-statement #[768 "\206�\302\303\206 �e`\304\212b\210\305`\304\211$)\262\203=�\3068\2045�\3078\2045�\310\311 \312Q!\203=�\313[!\210\202N�\314V\203N�\315!\210S\262\202=�`]b)\266\316 \207" [case-fold-search comment-start-skip 1 t nil parse-partial-sexp 3 4 looking-at "[ ]*\\(?:" "\\)" forward-sentence 0 vhdl-beginning-of-statement-1 vhdl-keep-region-active] 13 (#$ . 228465) "p\np"]) (defconst vhdl-e-o-s-re (concat ";\\|" vhdl-begin-fwd-re "\\|" vhdl-statement-fwd-re))#@29 Very simple implementation. (defalias 'vhdl-end-of-statement #[0 "\301!\207" [vhdl-e-o-s-re re-search-forward] 2 (#$ . 229525) nil]) (defconst vhdl-b-o-s-re (concat ";[^_]\\|([^_]\\|)[^_]\\|\\bwhen\\b[^_]\\|" vhdl-begin-bwd-re "\\|" vhdl-statement-bwd-re))#@162 Move to the start of the current statement. If already at the beginning of a statement, move to the start of the previous statement instead. (fn &optional LIM) (defalias 'vhdl-beginning-of-statement-1 #[256 "\211\206�e``\305\3061�\307 \210\3100\202�\210\305\204'�\311\312!\210\305u\210\313!\210\310\262\211?\205Co?\205C\305u\210\314\315#\205Ch\316U\204G�\317 \203M�\320u\210\202'�g\321=\203`�\305u\210\313!\210\310\262\202'�g\322=\203\202�\305u\210`\262\307 \210`W\203'�b\210\313!\210\310\262\202'�g\323=\203\232�\324 \204\232�\305u\210\313!\210\310\262\202'�\325 !\203\366�\325\326!\203\261�\212\327 \210\325\330!)\203\366�h\316U\204\366�\331\305!\203\366�\325\n!\203\334�\212`\262\332 b\210\313!\210`W\203\330�`\262)\202\355�\325\333!\204\346�\334\312!\210\313!\210`\262b\210\310\262\202'�\325 !\203h\316U\204\335\305!\203\310\262\202'�\325\f!\203=\336!\203=\212`\262\325\f!\210\337\225b\210\313!\210`W\2033`\262)b\210\310\262\202'�\320u\210\202'�\207" [vhdl-b-o-s-re vhdl-begin-fwd-re vhdl-leader-re vhdl-statement-fwd-re vhdl-case-alternative-re nil (error) backward-sexp t backward-up-list 1 vhdl-forward-syntactic-ws re-search-backward move 95 vhdl-in-literal -1 40 41 59 vhdl-in-quote-p looking-at "\\<use\\>" back-to-indentation "\\(\\w+\\s-*:\\s-*\\)?\\<\\(case\\|elsif\\|if\\)\\>" vhdl-begin-p vhdl-end-of-leader "\\<else\\s-+generate\\>" forward-word-strictly vhdl-statement-p vhdl-case-alternative-p 0] 9 (#$ . 229789)])#@145 If there is an enclosing library unit at BOD, with its "begin" keyword at PLACEHOLDER, then return the library unit type. (fn BOD PLACEHOLDER) (defalias 'vhdl-get-library-unit #[514 "`\300 \210`b\210\262\212b\210\3011�\302\303\"0\210\202�\210\211`X)\205m�\212b\210\304\305!\2031�\306\202l�\304\307!\203;�\310\202l�\304\311!\203E�\312\202l�\304\313!\203O�\314\202l�\304\315!\205l�\212b\210\316 \210\317!\210\304\320!\203j�\321\202k�\322))\207" [beginning-of-line (error) vhdl-forward-sexp 1 looking-at "e" entity "a" architecture "conf" configuration "cont" context "p" forward-sexp vhdl-forward-syntactic-ws "body\\b[^_]" package-body package] 6 (#$ . 231273)])#@149 Find and records all the closest opens. LIM is the furthest back we need to search (it should be the previous libunit keyword). (fn &optional LIM) (defalias 'vhdl-get-block-state #[256 "`\206�e\300\211\211\211\211\211\211\211\211\212\214 `}\210\3011#�\302`\303\304#0\202%�\210\300)\211\262\203/�\211\262\n`\nV\203\274�\204\274�\305\n!\262 \306\267\202/�`\262\307\n!\262\3101a�\212\311\304 \"\210`)0\202c�\210\300\262\203{� X\203{�\204/�\262\202/�\262\262\312\262\202/�\313 \210`\262\300\262\3141\241�\315\304 \"\210`0\202\245�\210\202\250�\206\254�\316 \210`\262\204/�\262\202/�\202/�)\211\203\327�\203\313�W\203\327�\211\262\300\262\300\262\300\262\317$\207" [nil (error) scan-lists -1 1 vhdl-backward-to-block #s(hash-table size 2 test eq rehash-size 1.5 rehash-threshold 0.8125 purecopy t data (begin 71 end 137)) vhdl-corresponding-mid (error) vhdl-forward-sexp t forward-sexp (error) vhdl-backward-sexp backward-sexp vector] 17 (#$ . 231951)]) (defconst vhdl-s-c-a-re (concat vhdl-case-alternative-re "\\|" vhdl-case-header-key))#@164 Skip forward over case/when bodies, with optional maximal limit. If no next case alternative is found, nil is returned and point is not moved. (fn &optional LIM) (defalias 'vhdl-skip-case-alternative #[256 "\211\206�d`\301\211`W\203U�\204U�\302\303#\203�\304 \305\306\"\216\307 )?\262\203�\310\224U\204�\310\224b\210\311\312!\203L�\302\313\314#\203L�\315 \210\316 \210\202�\314\262\314\262\202�\211\204\\�b\210\207" [vhdl-s-c-a-re nil re-search-forward move match-data make-closure #[0 "\301\300\302\"\207" [V0 set-match-data t] 3] vhdl-in-literal 0 looking-at "case" "\\bis[^_]" t backward-sexp vhdl-forward-sexp] 9 (#$ . 233041)])#@141 Skip backward over a label, with optional maximal limit. If label is not found, nil is returned and point is not moved. (fn &optional LIM) (defalias 'vhdl-backward-skip-label #[256 "\211\206�e\301\212\302!\210h\303=\205�\304 \210`\262\305!)\205 �\211b\207" [vhdl-label-key nil vhdl-backward-syntactic-ws 58 backward-sexp looking-at] 5 (#$ . 233698)])#@140 Skip forward over a label, with optional maximal limit. If label is not found, nil is returned and point is not moved. (fn &optional LIM) (defalias 'vhdl-forward-skip-label #[256 "\211\206�d\301!\205�\302\225b\210\303!\207" [vhdl-label-key looking-at 0 vhdl-forward-syntactic-ws] 4 (#$ . 234061)])#@67 Guess the syntactic description of the current line of VHDL code. (defalias 'vhdl-get-syntactic-context #[0 "\212\214\306 \210`\307\310\211\211\211\211\211\211\211\211\211\211\211\211\211\211\212\311 \262`)\262\2035�\312\"\211\262\2035�\211B B\313!\211\262\203V� \314H\262\f \315H\262  \316H\262\n \317H\262  \203x�\212 b\210\320\n!\203j�\321 \262`\306 \210`b)\210\262\202y�e\262b\210\322\310w\210\323 \262 g\262\f?\205\251�\320 !\205\251�\320\324!\203\247�\212\325 \210\320\326!)\205\251�\327 \262\f?\205\271�\320\f!\205\271�\330 \262\331!\210h\262b\210\322\310w\210\f\332>\203\344�\f`\333y\210`b\210\262B B\202\322 \204f\212\n\204\366�\334!\210\202 \nb\210``\325 \210`b\210\262U\204 \334!\210o\203\335!\210`)\262\203'\336B B\202\322\2034\337B B\202\322\331!\210o\204Gh\340U\203P\341 \204P\342B B\202\322\334!\210o\203]\335!\210\343`B B\202\322 \204\331\f!\210\344=\203\214 b\210\345`\325 \210`b\210\262B B\202\322\346=\203\251 b\210\347`\325 \210`b\210\262B B\202\322\212 Tb\210\322\310w\210\320\350!)\204\371\212\334\f!\210\351\310x\210h\340U\203\333\341 \204\333\334\f!\210\351\310x\210\202\304`\fX)\203\371 b\210\352`\325 \210`b\210\262B B\202\322\334\f!\210\335!\210\353`\325 \210`b\210\262B B\202\322\203G\320 !\203G b\210\320 !\2031\354 \210\334\310!\210\355`\325 \210`b\210\262!\210\336`B B\202\322\203r b\210\320 !\203\\\354 \210\334\310!\210\355`\325 \210`b\210\262!\210\337`B B\202\322\340U\204\203\214\320 !\204\212\355\f!)\204\320<!\203\230\356 \204\212\334 !\210\335!\210`)\211\262V\203\fU\204\212b\210\320=!?\206\306\314\225V)\203\212b\210\357!\210`)\211\262V\203\360\212\211b\210\211\325 \210`)=\203\360\211\262\210\343B B\203\322\336C B\202\322\320=!\2034\360\f!\2034 b\210\320 !\203\"\354 \210\334\310!\210\361`\325 \210`b\210\262B B\202\322\203@b\210\202G b\210\354 \210\335!\210`\262\310\320=!\203u`\262\362!\204Z\320=!\210\314\225b\210\335!\210`\262\202P\211\203\212`U\203\212\363B B\210\202\322`W\203\244\342B B\203\321\336C B\210\202\322\fb\210\320 !\203\265\354 \210\334\310!\210\355`\325 \210`b\210\262!\210\364`B B\203\321\336C B\210b\210\322\310w\210\320\365!\204\346\320\366!\203\353\367C B\320\370!\203\366\371C B\f\372=\203\373C B )\266\217*\207" [case-fold-search vhdl-syntactic-context vhdl-leader-re vhdl-begin-fwd-re vhdl-end-fwd-re vhdl-trailer-re beginning-of-line t nil vhdl-beginning-of-libunit vhdl-get-library-unit vhdl-get-block-state 0 1 2 3 looking-at vhdl-end-of-leader " " vhdl-in-literal "\\<use\\>" back-to-indentation "\\(\\w+\\s-*:\\s-*\\)?\\<\\(case\\|elsif\\|if\\)\\>" vhdl-begin-p vhdl-end-p vhdl-backward-syntactic-ws (string comment) -1 vhdl-beginning-of-statement-1 vhdl-forward-syntactic-ws block-open block-close 59 vhdl-in-quote-p statement statement-cont 41 arglist-close 40 arglist-intro "--\\|`" " (" arglist-cont-nonempty arglist-cont forward-sexp vhdl-backward-skip-label vhdl-statement-p vhdl-forward-skip-label vhdl-case-alternative-p case-alternative vhdl-skip-case-alternative statement-case-intro statement-block-intro "--" "/\\*" comment "`" directive pound cpp-macro vhdl-statement-fwd-re vhdl-case-alternative-re] 20 (#$ . 234369)])#@133 Lineup the current arglist line with the arglist appearing just after the containing paren which starts the arglist. (fn LANGELEM) (defalias 'vhdl-lineup-arglist #[257 "\212\212\211@\300>\203 �\301 \210\302\303!\210\304`\305\210`b\210\262w\210\202$�\211Ab\210`)\212Ab\210i)\212\301 \210\306\307!)\203M�\310\225b\210\311 \210\305u\210\312 \210iZ\266\202\202y�b\210l\204t�`\305\210`b\210\262\305u\210\304\305w\210`\312 \210`W\203r�\211b\210\266iZ\266\202)\207" [(arglist-intro arglist-cont-nonempty) beginning-of-line backward-up-list 1 " " nil looking-at "[ ]*)" 0 backward-sexp vhdl-forward-syntactic-ws] 7 (#$ . 237733)])#@75 Lineup an arglist-intro line to just after the open paren. (fn LANGELEM) (defalias 'vhdl-lineup-arglist-intro #[257 "\212\212\211Ab\210i)\212\300 \210\301\302!\210\303`\304\210`b\210\262w\210i)\211ZT\266\202)\207" [beginning-of-line backward-up-list 1 " " nil] 6 (#$ . 238376)])#@149 Support old behavior for comment indentation. We look at `vhdl-comment-only-line-offset' to decide how to indent comment only-lines. (fn LANGELEM) (defalias 'vhdl-lineup-comment #[257 "\212\302 \210iY\203�\303 \2021�n\204&�\304\305!\203�\306\2021� \242\2061� \2021� \243\2061� \242\2061�\307)\207" [comment-column vhdl-comment-only-line-offset back-to-indentation vhdl-comment-indent looking-at "\\*" 1 -1000] 3 (#$ . 238667)])#@70 Line up statement-cont after the assignment operator. (fn LANGELEM) (defalias 'vhdl-lineup-statement-cont #[257 "\212\211A\212`\301 \210`b\210\262b\210\302\303`\304\210`b\210\262\305#\205-�``\301 \210`b\210\262Z)b\210i\304\211\204\204�``\304\210`b\210\262W\203\204�\302\306`\304\210`b\210\262\307#\210\310 \203`�\304u\210\2023�h\311U\203{�`\304\210`b\210\262\312`\313\211#^b\210\2023�\314\315!?\262\2023�\211\204\216�\266\204\202\243�\204\234�\304u\210\316\304w\210\317\262iZZ\266\204)\207" [vhdl-basic-offset back-to-indentation re-search-forward "\\(<\\|:\\|=\\)=" nil t "\\(<\\|:\\|=\\)=\\|(" move vhdl-in-literal 40 scan-lists 1 looking-at "\\s-*$" " " 0] 10 (#$ . 239104)])#@66 Holds the progress reporter data during long running operations. (defvar vhdl--progress-reporter nil (#$ . 239813))#@309 If preceding character is part of a word or a paren then hippie-expand, else if right of non whitespace on line then insert tab, else if last command was a tab or return then dedent one step or if a comment toggle between normal indent and inline comment indent, else indent `correctly'. (fn &optional ARG) (defalias 'vhdl-electric-tab #[256 "\306\307 p\310\311#\216\312 !\210\313 \203�\314\315 \316 \317#\210\202\301�hz\320U\203?�\n?\317\321\303!\2033� \2064�\322\323!+\210\202\301�h\324U\204K�h\325U\203X�\n?\317\326!*\210\202\301�i\327 V\203e�\330 \210\202\301�\331\332!\203\241� \333=\204w� \334=\203\241�\327 \335U\203\207�\336j\210\337 \210\202\301�\327 \"W\203\231�\"j\210\337 \210\202\301�\340 `|\210\202\301�\327 #Y\203\276� \333=\204\265� \334=\203\276�\341#\317\"\210\202\301�\337 \210\333\211$)\266\202)\207" [case-fold-search vhdl-mode-ext-syntax-table vhdl-word-completion-case-sensitive hippie-expand-only-buffers case-replace last-command t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table use-region-p indent-region region-beginning region-end nil 119 boundp (vhdl-mode) vhdl-expand-abbrev 40 41 vhdl-expand-paren current-indentation insert-tab looking-at "--" vhdl-electric-tab vhdl-electric-return 0 1 indent-according-to-mode line-beginning-position backward-delete-char-untabify comment-column vhdl-basic-offset this-command] 7 (#$ . 239935) "*P"])#@101 `newline-and-indent' or `indent-new-comment-line' if in comment and preceding character is a space. (defalias 'vhdl-electric-return #[0 "h\300U\203�\301 \203�\302 \207h\303Y\203#�h\304X\203#�\301 \204#�\305\306!\210\307 \207" [32 vhdl-in-comment-p indent-new-comment-line 97 122 vhdl-fix-case-word -1 newline-and-indent] 2 (#$ . 241381) nil])#@80 Indent the current line as VHDL code. Return the amount of indentation change. (defalias 'vhdl-indent-line #[0 "\205�\305 d`Z\306\203W�@@\307=\203&�\310@! Y\203&�\310@!\202d�\n\203B�\212@@\307=\203A�\311\262\312\313!\210\305 \262\202+�)\211\203L�\307CB\262\314\315\316\310\"\"\202d�\212\312 \210\317\320\306\311#\210\321 )\211\321 Z \203s�\322\323#\210\212\312 \210\324\325!)\326U\203\205�\211\203\250�`\312 \210`b\210\262`\327 \210`b\210\262|\210\312 \210\211\203\245�\330c\210j\210\210``\327 \210`b\210\262W\203\276�\327 \210\202\313�dZ`V\203\313�dZb\210\331\332!\210\f\203\351�\f`\306\247\203\342�@Y\205\347�\333#\266\207" [vhdl-indent-syntax-based comment-column vhdl-indent-comment-like-next-code-line vhdl-echo-syntactic-information-p vhdl--progress-reporter vhdl-get-syntactic-context nil comment vhdl-get-offset t beginning-of-line 2 apply + mapcar re-search-backward "^[^\n]" current-indentation message "syntax: %s, indent= %d" looking-at "\\s-*\f" 0 back-to-indentation "\f" run-hooks vhdl-special-indent-hook progress-reporter-do-update] 12 (#$ . 241731) nil]) (byte-code "\300\301\302\303#\210\304\301\302\305#\207" [defalias vhdl-indent-region indent-region nil make-obsolete "28.1"] 4)#@103 Indent whole buffer as VHDL code. Calls `indent-region' for whole buffer and adds progress reporting. (defalias 'vhdl-indent-buffer #[0 "\300ed\"\207" [indent-region] 3 (#$ . 242971) nil])#@44 Indent group of lines between empty lines. (defalias 'vhdl-indent-group #[0 "\212\301\302\303#\203�\304 \202�\305 )\212\306\302\303#\203�\304 \202!�\307 )\310\"\207" [vhdl-align-group-separate re-search-backward nil t point-marker point-min-marker re-search-forward point-max-marker indent-region] 5 (#$ . 243165) nil])#@168 Indent each line of the list starting just after point. If optional arg ENDPOS is given, indent each line, stopping when ENDPOS is encountered. (fn &optional ENDPOS) (defalias 'vhdl-indent-sexp #[256 "\212`\300\301\"\210`\302\301#\266\202)\207" [vhdl-forward-sexp nil indent-region] 7 (#$ . 243498) nil])#@46 Show syntactic information for current line. (defalias 'vhdl-show-syntactic-information #[0 "\300\301\302 \"\210\303 \207" [message "Syntactic analysis: %s" vhdl-get-syntactic-context vhdl-keep-region-active] 3 (#$ . 243812) nil])#@67 Check syntactic information for current line. (fn &optional ARG) (defalias 'vhdl-regress-line #[256 "\212\300\210\301\302`\303 \210`b\210\262\304#\205�\305u\210\306p!)\307 \300C\310\311\312\"\"\210\204G�\203G�<\203G�\242\232\204u�\313\314\242#\266\202w�\212\303 \210\315\316!\204t�\300\210\301\302`\303 \210`b\210\262\304#\203j�`\317 |\210\320c\210\321\322\242\"c\210)\266\323 \207" [nil search-backward " -- ((" beginning-of-line t 4 read vhdl-get-syntactic-context mapc make-closure #[257 "\211@\301>?\205�\300\302\300\242C\"\240\207" [V0 (entity configuration context package package-body architecture) append] 5 "\n\n(fn ELT)"] error "ERROR: Should be: %s, is: %s" looking-at "^\\s-*\\(--.*\\)?$" line-end-position " -- " format "%s" vhdl-keep-region-active] 9 (#$ . 244048) "P"])#@469 The format of this alist is (MODES [or MODE] REGEXP ALIGN-PATTERN SUBEXP). It is searched in order. If REGEXP is found anywhere in the first line of a region to be aligned, ALIGN-PATTERN will be used for that region. ALIGN-PATTERN must include the whitespace to be expanded or contracted. It may also provide regexps for the text surrounding the whitespace. SUBEXP specifies which sub-expression of ALIGN-PATTERN matches the white space to be expanded/contracted. (defconst vhdl-align-alist '((vhdl-mode "^\\s-*\\(across\\|constant\\|quantity\\|signal\\|subtype\\|terminal\\|through\\|type\\|variable\\)[ ]" "^\\s-*\\(across\\|constant\\|quantity\\|signal\\|subtype\\|terminal\\|through\\|type\\|variable\\)\\([ ]+\\)" 2) (vhdl-mode ":[^=]" "\\([ ]*\\):[^=]") (vhdl-mode ":[ ]*\\(in\\|out\\|inout\\|buffer\\|\\)\\>" ":[ ]*\\(in\\|out\\|inout\\|buffer\\|\\)\\([ ]+\\)" 2) (vhdl-mode "[<:=]=" "\\([ ]*\\)\\??[<:=]=" 1) (vhdl-mode "=>" "\\([ ]*\\)=>" 1) (vhdl-mode "[<:=]=" "\\([ ]*\\)\\??[<:=]=" 1) (vhdl-mode "[ ]after\\>" "[^ ]\\([ ]+\\)after\\>" 1) (vhdl-mode "[ ]when\\>" "[^ ]\\([ ]+\\)when\\>" 1) (vhdl-mode "[ ]else\\>" "[^ ]\\([ ]+\\)else\\>" 1) (vhdl-mode "[ ]across\\>" "[^ ]\\([ ]+\\)across\\>" 1) (vhdl-mode "[ ]through\\>" "[^ ]\\([ ]+\\)through\\>" 1) (vhdl-mode "=>" "\\([ ]*\\)=>" 1)) (#$ . 244862))#@142 If REGEXP is not found on the first line of the region that clause is ignored. If this variable is non-nil, then the clause is tried anyway. (defvar vhdl-align-try-all-clauses t (#$ . 246211))#@88 Apply FUNCTION on group of lines between empty lines. (fn FUNCTION &optional SPACING) (defalias 'vhdl-do-group #[513 "\212\301\302\303#\203�\304\305!\210\306 \210`\202�e)\212\307\302\303#\203&�\304 \210`\202'�d)#\207" [vhdl-align-group-separate re-search-backward nil t beginning-of-line 2 back-to-indentation re-search-forward] 8 (#$ . 246409)])#@115 Apply FUNCTION to lines of a list surrounded by a balanced group of parentheses. (fn FUNCTION &optional SPACING) (defalias 'vhdl-do-list #[513 "\300\211\212\301\302\300\303#\262\304\305!\203 �\300u\210\306 \210\301\302\300\303#\262\202\n�\2035�\307 \210`\262Tb\210\310\300w\210`\262)\203@�#\207\311\312!\207" [nil vhdl-re-search-backward "[()]" t looking-at ")" backward-sexp forward-list " \n \f" error "ERROR: Not within a list enclosed by a pair of parentheses"] 8 (#$ . 246771)])#@85 Apply FUNCTION to block of lines with same indent. (fn FUNCTION &optional SPACING) (defalias 'vhdl-do-same-indent #[513 "\300 \301\211\212o\204)�\302\303!\204�\300 U\203)�\302\304!\204\"�\305 \210`\262\306\307!\210\202�)\212m\204S�\302\303!\204<�\300 U\203S�\302\304!\203I�\306\310!\210\202+�\306\310!\210`\262\202+�)#\207" [current-indentation nil looking-at "^\\s-*\\(--.*\\)?$" "^\\s-*$" back-to-indentation beginning-of-line 0 2] 9 (#$ . 247274)])#@362 Attempt to align a range of lines based on the content of the lines. The definition of `alignment-list' determines the matching order and the manner in which the lines are aligned. If ALIGNMENT-LIST is not specified `vhdl-align-alist' is used. If INDENT is non-nil, indentation is done before aligning. (fn BEGIN END &optional SPACING ALIGNMENT-LIST INDENT) (defalias 'vhdl-align-region-1 #[1282 "\206�\262\206\f�\305\262\212\306b\210\307 \262b\210\310 \210`\211\262\266)\311!\312\313 p\314\315#\216\316\n!\210\205\204�\212b\210\306\317 @\262@<\203S� @>\204Z� @=\203z�\f\204h�\320A@\312#\203z�\321\n\nAA@AAA@\f%\210A)\262\266\2026�)\266\202)\207" [vhdl-align-alist case-fold-search vhdl-mode-ext-syntax-table major-mode vhdl-align-try-all-clauses 1 nil point-marker beginning-of-line copy-alist t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table line-end-position re-search-forward vhdl-align-region-2] 16 (#$ . 247744) "r\np"])#@446 Align a range of lines from BEGIN to END. The regular expression MATCH must match exactly one field: the whitespace to be contracted/expanded. The alignment column will equal the rightmost column of the widest whitespace block. SPACING is the amount of extra spaces to add to the calculated maximum required. SPACING defaults to 1 so that at least one space is inserted after the token in MATCH. (fn BEGIN END MATCH &optional SUBSTR SPACING) (defalias 'vhdl-align-region-2 #[1283 "\211\206�\300\262\206\f�\300\262\212\301\302\211\301\211\211\nb\210\303 \262\304 \210`\211\262\f\262\nW\203z�\212\305 \306#\203h�\212\302\224b\210\301u\210\307 ?\205N�\310 ?\205N�\311 ?)\203h�\312\313!\204h�\224Z\262V\203h�\262)\301y\210`\262\303 \262T\262\202&�\n\211\262b\210\303 \262\302V\205\372�\305 \306#\203\346�\212\302\224b\210\301u\210\307 ?\205\253�\310 ?\205\253�\311 ?)\203\346�\312\313!\204\346�\302\224\212\314 \210`)V\203\346�\225\224Z\262\224Z\262\224b\210\315!\210\316\317Z \\\"\210\304 \210\301y\210`\262\303 \262S\262\202\205�\266\206)\207" [1 nil 0 line-end-position beginning-of-line vhdl-re-search-forward t vhdl-in-literal vhdl-in-quote-p vhdl-in-extended-identifier-p looking-at "\\s-*$" back-to-indentation delete-char insert-char 32] 15 (#$ . 248768)])#@104 Align region, treat groups of lines separately. (fn BEG END &optional SPACING NO-MESSAGE NO-COMMENTS) (defalias 'vhdl-align-region-groups #[1282 "\212b\210\306 \210`\262b\210\307 \262\310\"\210\311!\312\203\"�\202/� \205/�\313\314\311 !#\n@\203=�\315\316#\210b\210 \204\\�\317#\210\204\336�\320\"\210\202\336�W\203\250�\321\f\316#\203\250�\307 \262\317#\210\204\203�\320\"\210\203\235�`\312\247\203\226�@Y\205\233�\322#\266\211T\262b\210\202\\�W\203\336�\317#\210\204\304�\320\"\210\203\336�`\312\247\203\327�@Y\205\334�\322#\266 \203\350�\323\"\210?\205\364�\205\364�\324!)\266\202)\207" [vhdl--progress-reporter vhdl-progress-interval vhdl-beautify-options vhdl-align-groups vhdl-align-group-separate vhdl-indent-tabs-mode beginning-of-line point-marker untabify copy-marker nil make-progress-reporter "Aligning..." vhdl-fixup-whitespace-region t vhdl-align-region-1 vhdl-align-inline-comment-region-1 re-search-forward progress-reporter-do-update tabify progress-reporter-done] 14 (#$ . 250088) "r\nP"])#@108 Align region, treat blocks with same indent and argument lists separately. (fn BEG END &optional SPACING) (defalias 'vhdl-align-region #[770 "\204\n�\304#\207\212\305\211 \205�\306\307\310!#b\210\311 \262b\210`W\203\267�\212\312``\305\210`b\210\262\")A@\211\262\203S�b\210\313 \210`\262\314\315!\210\202\253�\316 \262`\262`\317y\210`b\210\262\262\314\315!\210`W\203\253�\320\321!\204}�\316 U\203\253�\212\312``\305\210`b\210\262\"@)\322X\203\253�\320\323!\204\244�`\317y\210`b\210\262\262\314\315!\210\202j�\304\324\211%\210\202&�\325 $\210\n\205\310�\326\n!)\266\203)\207" [vhdl-align-same-indent vhdl-progress-interval vhdl--progress-reporter noninteractive vhdl-align-region-groups nil make-progress-reporter "Aligning..." copy-marker point-marker parse-partial-sexp forward-sexp beginning-of-line 2 current-indentation 1 looking-at "^\\s-*\\(--.*\\)?$" 0 "^\\s-*$" t vhdl-align-inline-comment-region progress-reporter-done] 12 (#$ . 251190) "r\nP"])#@67 Align group of lines between empty lines. (fn &optional SPACING) (defalias 'vhdl-align-group #[256 "\300\301\"\207" [vhdl-do-group vhdl-align-region] 4 (#$ . 252194) nil])#@98 Align the lines of a list surrounded by a balanced group of parentheses. (fn &optional SPACING) (defalias 'vhdl-align-list #[256 "\300\301\"\207" [vhdl-do-list vhdl-align-region-groups] 4 (#$ . 252373) nil])#@64 Align block of lines with same indent. (fn &optional SPACING) (defalias 'vhdl-align-same-indent #[256 "\300\301\"\207" [vhdl-do-same-indent vhdl-align-region-groups] 4 (#$ . 252588) nil])#@87 Align the lines within the declarative part of a design unit. (fn &optional SPACING) (defalias 'vhdl-align-declarations #[256 "\302\211\303\304 p\305\306#\216\307 !\210\212\310\311\302\303#\203/�\312\313!\226\314\235\204/�`\262\315\316\302\303#\210`\262+\266\203<�\317#\207\320\321!\207" [case-fold-search vhdl-mode-ext-syntax-table nil t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table re-search-backward "^\\(architecture\\|begin\\|configuration\\|context\\|end\\|entity\\|package\\)\\>" match-string 1 ("BEGIN" "END") re-search-forward "^\\(begin\\|end\\)\\>" vhdl-align-region-groups error "ERROR: Not within the declarative part of a design unit"] 9 (#$ . 252783) nil])#@15 Align buffer. (defalias 'vhdl-align-buffer #[0 "\300ed\"\207" [vhdl-align-region] 3 (#$ . 253529) nil])#@66 Align inline comments in region. (fn BEG END &optional SPACING) (defalias 'vhdl-align-inline-comment-region-1 #[770 "\212\304\305\211\211\211\211\211\211\211\n\206�\306\262 \307\310 p\311\312#\216\313\n!\210b\210`W\203s�\314\315!\204l�\314\316!\203l�\212\306\224b\210\317 )\204l�\320\225\320\224Z \\\262\306\225\306\224Z\262\f]\262\f ]\262 B\nB\262\n\321\306!\210\202&�\322\n\323\"\262\n @@C\262  A\262\n \203\264� @@ @U\204\254�@\n@A\\ X\204\254� @@ B\262  A\262\n\202\206�b\210`W\205s\305\262\314\315!\204i\314\324!\203\331�\212\325\224b\210\317 )\203\351�\314\326!\203i\306\225\306\224ZY\203i\320\225\320\224Z \\\262\325\225\325\224Z\262\320\224\320\225U\262\306\225b\210\306\224\306\225|\210\327\330\"\210\262\203)\203) ZX\203)\202d  \\ X\2038 \202dX\203K ZX\203K\202d\203a@W\203aA\262\202K@\262j\210\262\321\306!\210\202\270�)\266\202)\266\212)\207" [comment-column case-fold-search vhdl-mode-ext-syntax-table end-comment-column 0 nil 2 t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table looking-at "^\\s-*\\(begin\\|end\\)\\>" "^\\(.*?[^ \n \f-]+\\)\\s-*\\(--.*\\)$" vhdl-in-literal 1 beginning-of-line sort #[514 "@@V\207" [] 4 "\n\n(fn A B)"] "^\\(.*?[^ \n \f-]+\\)\\(\\s-*\\)\\(--.*\\)$" 3 "^\\(\\)\\(\\s-*\\)\\(--.*\\)$" insert-char 32] 19 (#$ . 253638)])#@190 Align inline comments within a region. Groups of code lines separated by empty lines are aligned individually, if `vhdl-align-groups' is non-nil. (fn BEG END &optional SPACING NO-MESSAGE) (defalias 'vhdl-align-inline-comment-region #[1026 "\212\303\211b\210\304 \210\305 \262`\262b\210\305 \262\306\"\210\204&�\307\310!\210b\210\2049�\311#\210\202m�W\203^�\312 \313#\203^�\305 \262\311#\210\211T\262b\210\2029�W\203m�\311#\210\n\203w�\314\"\210?\205�\307\315!\266\202)\207" [vhdl-align-groups vhdl-align-group-separate vhdl-indent-tabs-mode nil beginning-of-line point-marker untabify message "Aligning inline comments..." vhdl-align-inline-comment-region-1 re-search-forward t tabify "Aligning inline comments...done"] 10 (#$ . 255063) "r\nP"])#@92 Align inline comments within a group of lines between empty lines. (fn &optional SPACING) (defalias 'vhdl-align-inline-comment-group #[256 "\212`\302\211\303\302\304#\203�\305 \202�d\262b\210\306\302\304#\203#�`\202$�e\262\307\"\210\310\311!\210\312\"\210 \203=�\313\"\210\310\314!\266\203)\207" [vhdl-align-group-separate vhdl-indent-tabs-mode nil re-search-forward t point-marker re-search-backward untabify message "Aligning inline comments..." vhdl-align-inline-comment-region-1 tabify "Aligning inline comments...done"] 8 (#$ . 255858) nil])#@145 Align inline comments within buffer. Groups of code lines separated by empty lines are aligned individually, if `vhdl-align-groups' is non-nil. (defalias 'vhdl-align-inline-comment-buffer #[0 "\300ed\"\207" [vhdl-align-inline-comment-region] 3 (#$ . 256425) nil])#@230 Fixup whitespace in region. Surround operator symbols by one space, eliminate multiple spaces (except at beginning of line), eliminate spaces at end of line, do nothing in comments and strings. (fn BEG END &optional NO-MESSAGE) (defalias 'vhdl-fixup-whitespace-region #[770 "\211\204�\300\301!\210\212b\210\302 \262b\210\303\304\305#\2033�\306\307!\203(�\307\225b\210\202�\310\311\312\211\211\313%\210\202�b\210\303\314\305#\203R�\306\307!\203K�\307\225b\210\2026�\310\315!\210\2026�b\210\303\316\305#\203q�\306\307!\203j�\307\225b\210\202U�\310\315!\210\202U�b\210\303\317\305#\203\240�\306\307!\204\216�\320\224\212\321 \210`)X\203\225�\320\225b\210\202t�\310\322!\210\313\225b\210\202t�b\210\323\324!\203\261�\303\324\305#\204\243�\323\325!\203\277�\303\325\305#\204\243�\323\326!\203\315�\303\327\305#\204\243�\323\330!\203\344�\303\330\305#\203\344�\310\331\312\211#\210\202\243�\323\332!\203\373�\303\332\305#\203\373�\310\333\312\211#\210\202\243�\323\334!\203 \303\334\305#\204\243�\323\335!\203 \303\336\305#\203 \310\337\312\211#\210\202\243�\323\336!\2037\303\336\305#\2037\310\340\312\211#\210\202\243�\323\341!\203E\303\341\305#\204\243�\303\342\305#\204\243�)\211?\205V\300\343!\207" [message "Fixing up whitespace..." point-marker re-search-forward "\\(--.*\n\\|\"[^\"\n]*[\"\n]\\|'.'\\|\\\\[^\\\n]*[\\\n]\\)\\|\\(\\s-*\\([,;]\\)\\)" t match-string 1 replace-match "\\3 " nil 2 "\\(--.*\n\\|\"[^\"\n]*[\"\n]\\|'.'\\|\\\\[^\\\n]*[\\\n]\\)\\|\\((\\)\\s-+" "\\2" "\\(--.*\n\\|\"[^\"\n]*[\"\n]\\|'.'\\|\\\\[^\\\n]*[\\\n]\\|^\\s-+\\)\\|\\s-+\\()\\)" "\\(--.*\n\\|\"[^\"\n]*[\"\n]\\|'.'\\|\\\\[^\\\n]*[\\\n]\\)\\|\\(\\([^/:<>=\n]\\)\\(:\\|\\??=\\|\\??<<\\|\\??>>\\|\\??<\\|\\??>\\|:=\\|\\??<=\\|\\??>=\\|=>\\|\\??/=\\|\\?\\?\\)\\([^=>\n]\\|$\\)\\)" 0 back-to-indentation "\\3 \\4 \\5" looking-at "--.*\n" "--.*" "\"" "\"[^\"\n]*[\"\n]" "\\s-+$" "" "\\s-+;" ";" "^\\s-+" "\\s-+--" "\\s-+" " " " " "-" "[^ \"-]+" "Fixing up whitespace...done"] 9 (#$ . 256695) "r"])#@183 Fixup whitespace in buffer. Surround operator symbols by one space, eliminate multiple spaces (except at beginning of line), eliminate spaces at end of line, do nothing in comments. (defalias 'vhdl-fixup-whitespace-buffer #[0 "\300ed\"\207" [vhdl-fixup-whitespace-region] 3 (#$ . 258708) nil])#@162 Convert all words matching WORD-REGEXP in region to lower or upper case, depending on parameter UPPER-CASE. (fn BEG END UPPER-CASE WORD-REGEXP &optional COUNT) (defalias 'vhdl-fix-case-region-1 #[1284 "\305\205�\205� ?\205�\306\307\310!#\311\312 p\313\314#\216\315\f!\210\212b\210\316 \262b\210\317 \311#\203q�\320 \204T�\203P�\321\322!\210\202T�\323\322!\210\2035�`\305\247\203g�@Y\205l�\324#\266\2025�\205x�\325!*\266\202*\207" [vhdl-progress-interval noninteractive case-replace case-fold-search vhdl-mode-ext-syntax-table nil make-progress-reporter "Fixing case..." copy-marker t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table point-marker re-search-forward vhdl-in-literal upcase-word -1 downcase-word progress-reporter-do-update progress-reporter-done] 16 (#$ . 259008)])#@164 Convert all VHDL words in region to lower or upper case, depending on options vhdl-upper-case-{keywords,types,attributes,enum-values}. (fn BEG END &optional ARG) (defalias 'vhdl-fix-case-region #[770 "\306 \307%\210\306\n \310%\210\306\f\311 P\312%\210\306\313%\210\306\314%\210\2056�\315\316!\207" [vhdl-upper-case-keywords vhdl-keywords-regexp vhdl-upper-case-types vhdl-types-regexp vhdl-upper-case-attributes vhdl-attributes-regexp vhdl-fix-case-region-1 0 1 "'" 2 3 4 message "Fixing case...done" vhdl-upper-case-enum-values vhdl-enum-values-regexp vhdl-upper-case-constants vhdl-constants-regexp vhdl-progress-interval] 9 (#$ . 259883) "r"])#@136 Convert all VHDL words in buffer to lower or upper case, depending on options vhdl-upper-case-{keywords,types,attributes,enum-values}. (defalias 'vhdl-fix-case-buffer #[0 "\300ed\"\207" [vhdl-fix-case-region] 3 (#$ . 260559) nil])#@75 Convert word after cursor to upper case if necessary. (fn &optional ARG) (defalias 'vhdl-fix-case-word #[256 "\212\211\203�\306v\210\307\310 p\311\312#\216\313 !\210\n\203%�\314 !\203%�\315\316!\210\f\2033�\314 !\2033�\315\316!\210\203C�\314!\203C�\315\316!\210\203S�\314!\203S�\315\316!\210\205b�\314!\205b�\315\316!)\266\202*\207" [case-fold-search vhdl-mode-ext-syntax-table vhdl-upper-case-keywords vhdl-keywords-regexp vhdl-upper-case-types vhdl-types-regexp -1 t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table looking-at upcase-word 1 vhdl-upper-case-attributes vhdl-attributes-regexp vhdl-upper-case-enum-values vhdl-enum-values-regexp vhdl-upper-case-constants vhdl-constants-regexp] 7 (#$ . 260795) "p"])#@199 Force statements in region on separate line except when on same line with `end' keyword (necessary for correct indentation). Currently supported keywords: `begin', `if'. (fn BEG END &optional ARG) (defalias 'vhdl-fix-statement-region #[770 "\302\303 p\304\305#\216\306 !\210\307\212b\210\310 \262b\210\311\312\302#\203^�\313\225b\210\310 \262\314\315!\203X�\314\316!\203C�\212\316\225b\210\317 )\203X�\212\315\224b\210\317 )\204X�\315\224b\210\320c\210\321 \210\211b\210\202�b\210\311\322\302#\205\257�\315\225b\210\310 \262\212\315\224b\210\317 )\204\251�\212\323\315!\210\324 \304\325\"\216\311\326\315\224\302#\205\231�\327\330\314\315!\"?*\262\203\251�\315\224b\210\320c\210\321 \210\211b\210\202a�*\262\266\202)\207" [case-fold-search vhdl-mode-ext-syntax-table t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table nil point-marker re-search-forward "^\\s-*[^ \n].*?\\(\\<begin\\>\\)\\(.*\\<end\\>\\)?" 0 match-string 1 2 vhdl-in-literal "\n" indent-according-to-mode "\\<\\(for\\|if\\)\\>" beginning-of-line match-data #[0 "\301\300\302\"\207" [V0 set-match-data t] 3] "^\\s-*\\([^ \n].*\\)" string-match "\\(\\<end\\>\\|\\<wait .*\\|\\w+\\s-*:\\)\\s-*$"] 11 (#$ . 261587) "r"])#@126 Force statements in buffer on separate line except when on same line with `end' keyword (necessary for correct indentation). (defalias 'vhdl-fix-statement-buffer #[0 "\300ed\"\207" [vhdl-fix-statement-region] 3 (#$ . 262849) nil])#@63 Remove trailing spaces in region. (fn BEG END &optional ARG) (defalias 'vhdl-remove-trailing-spaces-region #[770 "\212b\210\300 \262b\210\301\302\303#\205!�\304 \204 �\305\306\307\211#\210\202 �)\207" [point-marker re-search-forward "[ ]+$" t vhdl-in-literal replace-match "" nil] 7 (#$ . 263085) "r"])#@35 Remove trailing spaces in buffer. (defalias 'vhdl-remove-trailing-spaces #[0 "\300ed\"\207" [vhdl-remove-trailing-spaces-region] 3 (#$ . 263399) nil])#@246 Beautify region by applying indentation, whitespace fixup, alignment, and case fixing to a region. Calls functions `vhdl-indent-buffer', `vhdl-align-buffer' (option `vhdl-align-groups' set to non-nil), and `vhdl-fix-case-buffer'. (fn BEG END) (defalias 'vhdl-beautify-region #[514 "\212\211b\210\303 )\262\212b\210\304\305\306\307#\203�\310\311\306\307#\210\202 �)@\203*�\312\307#\210A@\2035�\313\"\210\3148\203@�\315\"\210\3168\203N�\307\317\")\210\3208\203Y�\321\"\210@\205p�\322\"\210\n\203l�\323\"\207\324\"\207" [vhdl-beautify-options vhdl-align-groups vhdl-indent-tabs-mode point-marker search-forward " " nil t replace-match "" vhdl-fixup-whitespace-region vhdl-fix-statement-region 2 indent-region 3 vhdl-align-region 4 vhdl-fix-case-region vhdl-remove-trailing-spaces-region tabify untabify] 6 (#$ . 263556) "r"])#@158 Beautify buffer by applying indentation, whitespace fixup, alignment, and case fixing to entire buffer. Calls `vhdl-beautify-region' for the entire buffer. (defalias 'vhdl-beautify-buffer #[0 "\301ed\"\210\205 �\302 \207" [noninteractive vhdl-beautify-region save-buffer] 3 (#$ . 264413) nil])#@62 Fill lines for a region of code. (fn BEG END &optional ARG) (defalias 'vhdl-fill-region #[770 "\212b\210\211\203 �\301 \202�ib\210\302 \262\303\"\210\304\"\210\305S\306\307$\210\310\"\210b\210\311\312\313#\205R�iV\203/�\314u\210\315\312\313#\203/�\316\317!\210\211j\210\202/�)\207" [vhdl-end-comment-column current-indentation point-marker vhdl-comment-kill-region vhdl-comment-kill-inline-region subst-char-in-region 10 32 vhdl-fixup-whitespace-region re-search-forward "\\s-" t -1 re-search-backward replace-match "\n"] 9 (#$ . 264714) "r\np"])#@42 Fill group of lines between empty lines. (defalias 'vhdl-fill-group #[0 "\300\301!\207" [vhdl-do-group vhdl-fill-region] 2 (#$ . 265283) nil])#@73 Fill the lines of a list surrounded by a balanced group of parentheses. (defalias 'vhdl-fill-list #[0 "\300\301!\207" [vhdl-do-list vhdl-fill-region] 2 (#$ . 265431) nil])#@52 Fill the lines of block of lines with same indent. (defalias 'vhdl-fill-same-indent #[0 "\300\301!\207" [vhdl-do-same-indent vhdl-fill-region] 2 (#$ . 265608) nil])#@45 Update sensitivity list of current process. (defalias 'vhdl-update-sensitivity-list-process #[0 "\212\302\303 p\304\305#\216\306 !\210\307\210\310\311\307\302#\203.�\312\313!\226\314\232\203.�\212\315\316\307\302#)\2044�\317\320!\202>�\321\322!\210\323 \210\321\324!)\266\202*\207" [case-fold-search vhdl-mode-ext-syntax-table t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table nil re-search-backward "^\\s-*\\(\\w+[ \n \f]*:[ \n \f]*\\)?\\(process\\|end\\s-+process\\)\\>" match-string 2 "PROCESS" re-search-forward "^\\s-*end\\s-+process\\>" error "ERROR: Not within a process" message "Updating sensitivity list..." vhdl-update-sensitivity-list "Updating sensitivity list...done"] 6 (#$ . 265778) nil])#@61 Update sensitivity list of all processes in current buffer. (defalias 'vhdl-update-sensitivity-list-buffer #[0 "\212\303\304 p\305\306#\216\307 !\210eb\210\310\311!\210\312\313\314\303#\2032�\315\224b\210\3161.�\317 0\210\202�\210\202�\310\320!+\266\n\205>�\321 \207" [case-fold-search vhdl-mode-ext-syntax-table noninteractive t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table message "Updating sensitivity lists..." re-search-forward "^\\s-*\\(\\w+[ \n \f]*:[ \n \f]*\\)?process\\>" nil 0 (error) vhdl-update-sensitivity-list "Updating sensitivity lists...done" save-buffer] 6 (#$ . 266549) nil])#@26 Update sensitivity list. (defalias 'vhdl-update-sensitivity-list #[0 "`\302\303\304\305#\306\307\304\305#\304\310\311!\204�\312\313!\207b\210\314\315\305#\203%�\312\316!\207\317 \314\320\321BBB\314\322\323BBBD\314\324\325BBB\314\326\327BBBD\314\330\331BBB\314\326\332BBBD\314\333\334BBB\314\335 \336BBBD\314\337 \340BBB\314\341\n\342BBBD\314\343\n\344BBB\314\345 \346BBBD\314\347 \350BBB\314\351\f\352BBBD\353\302\354 \355BBB\356BB\357B\257\304\211\211\211\211\211\211\211\211\211\211b\210\314\360\305#\210\361\362!\204\317�`\262\202\375�\314\363\304\305#\262\364\225b\210\365 \210`S\262b\210\314\366\305#\203\375�\310\367!\227B\262\314\370\305#\204\344�\371  \"\262b\210\302\372\305#\211\262\203=\314\326\305#\262\306\373\305#\203 b\210\374\364!\210\375 \210`BB\262\376 \210\202  \203|b\210\377\f@@!\211\262\203t\377\f@A@!\211\262\203tb\210\201@� \204F \203\221 \211\203\203`@@W\203\203\211A\262\202p\211\205\214`@AW\262\204F\314\201A�\305#\203F\310\364!\262 \203\344\310\311!\262\n\201B� \201C�\201D�\"\216 \262\n\203\342\203\342\201E�\201F�@\201G�Q\f\"\203\332\304\262 A\262\202\272)\210\310\201H�!\204m\310\201I�!\203\310\201I�!\227\201J�\235\203m\n\227\235\203m\201K� \n\"\204-\201K�  P\n\"\204-\n\nP B\262 \262\201B� \201C�\201L�\"\216\203k\201E�\201M�  \201N�R@\"\203c\201O�@ \"\262\nA\262\202>)\210\364\225b\210\202\221 A\262\f\202=b\210\203\212|\210\202\231\203\231\201P�c\210\201Q�u\210\201R� \201S�\"\262 \205\352i\262@c\210A\262 \205\352\201T�c\210i @G\\\311\\ X\203\325\201U�c\210\202\335\201V�c\210\211j\210@c\210A\262 \202\266\207" [vhdl-array-index-record-field-in-sensitivity-list end-comment-column re-search-forward "^\\s-*end\\s-+process\\>" nil t vhdl-re-search-backward "\\(\\(\\<begin\\>\\)\\|^\\s-*process\\>\\)" match-string 2 error "ERROR: No 'begin' keyword found" vhdl-re-search-forward "\\<wait\\>" "ERROR: Process with wait statement, sensitivity list not generated" vhdl-get-visible-signals "[<:]=" (t) ";\\|\\<\\(then\\|loop\\|report\\|severity\\|is\\)\\>" (t) "^\\s-*if\\>" (t) "\\<then\\>" (t) "\\<elsif\\>" (t) (t) "^\\s-*while\\>" (t) "\\<loop\\>" (t) "\\<\\(exit\\|next\\)\\s-+\\w+\\s-+when\\>" (t) ";" (t) "\\<assert\\>" (t) "\\(\\<report\\>\\|\\<severity\\>\\|;\\)" (t) "^\\s-*case\\>" (t) "\\<is\\>" (t) and "^\\s-*\\(\\w\\|\\.\\)+[ \n \f]*(" (t) ((1- (point))) ((progn (backward-char) (forward-sexp) (while (looking-at "(") (forward-sexp)) (point))) "\\<process\\>" looking-at "[ \n \f]*(" "\\([ \n \f]*\\)([ \n \f]*" 1 forward-sexp "\\(\\w+\\)" 0 "\\s-*,\\s-*" append "^\\s-*\\(els\\)?if\\>" "\\('event\\|\\<\\(falling\\|rising\\)_edge\\)\\>" backward-word-strictly vhdl-forward-sexp beginning-of-line eval vhdl-in-literal "[^'\".]\\<\\([a-zA-Z]\\w*\\)\\(\\(\\.\\w+\\|[ \n \f]*([^)]*)\\)*\\)[ \n \f]*\\('\\(\\w+\\)\\|\\(=>\\)\\)?" match-data make-closure #[0 "\301\300\302\"\207" [V0 set-match-data t] 3] string-match "\\<" "\\>" 6 5 ("event" "last_event" "transaction") member-ignore-case #[0 "\301\300\302\"\207" [V0 set-match-data t] 3] "^" "[(.]" delete " ()" -1 sort string< "," " " "\n"] 23 (#$ . 267215)])#@47 Get all signals visible in the current block. (defalias 'vhdl-get-visible-signals #[0 "\303C\303C\303C\303C\303\304\305 p\306\307#\216\310 !\210\212\311\312\303\304#\2032�\313\314!\226\315\232\2042�\313\316!\240\2046�\317\320!\210)\212eb\210\321\322\242\323Q\303\304#\204U�\324\n\242\304#\325\326\327 !Q\262\330\304\306\331\n\f%#)\210\212\311\312\303\304#\240\203\205�\313\314!\226\315\232\204\205�\321\332\303\304#\240\204\214�\317\333!\210\202\354�\242b\210\321\334\242\304#\203\354�\335\242`\"@\336U\203\221�\313\316!\203\305�\337\340!\203\344�\313\314!\227\242B\240\210\336\225b\210\202\255�\337\341!\203\344�\313\316!\227\242\235\203\344�\313\314!\227\242B\240\210\336\225b\210`\240\210\202\221�)\212\311\342\303\304#\240\203\313\343!\203\343\225b\210\344 \210\311\345\303\304#\210\202\356�\242\203\202\321\346\303\304#\240\203\202\242b\210\321\334\242\304#\203z\335\242`\"@\336U\203$\313\316!\203X\337\347!\203$\313\314!\227\242B\240\210\336\225b\210\202@\337\350!\203$\313\316!\227\242\235\203$\313\314!\227\242B\240\210\336\225b\210\202$\242b\210\202\356�)\242)\266\202)\207" [case-fold-search vhdl-mode-ext-syntax-table vhdl-entity-file-name nil t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table re-search-backward "^\\(architecture\\s-+\\w+\\s-+of\\s-+\\(\\w+\\)\\|end\\)\\>" match-string 1 "END" 2 error "ERROR: Not within an architecture" re-search-forward "^entity\\s-+" "\\>" vhdl-replace-string "." file-name-extension buffer-file-name vhdl--visit-file #[0 "\306\307 p\310\311#\216\312 !\210eb\210\313\314\300\242\315Q\316\306#\204&�\317\320\300\242\"\202}�\303\321\322\212\313\323\316\306#)\306#\240\205}�\302\212\324u\210\325 \210`)\240\210\326 \210`\302\242W\205}�\327\330!\203V�\331\225b\210\327\332!\203p�\301\333\334!\227\301\242B\240\210\331\225b\210\326 \210\202V�\313\335\302\242\334#\210\326 \210\202E�)\266\202)\207" [V0 V1 V2 V3 case-fold-search vhdl-mode-ext-syntax-table t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table re-search-forward "^entity\\s-+" "\\>" nil error "ERROR: Entity \"%s\" not found:\n --> see option `vhdl-entity-file-name'" vhdl-re-search-forward "\\<port[ \n \f]*(" "^end\\>" -1 forward-sexp vhdl-forward-syntactic-ws looking-at "signal[ \n \f]+" 0 "\\([a-zA-Z]\\w*\\)[ \n \f,]+" match-string 1 ";"] 9] "^begin\\>" "ERROR: No architecture declarative part found" "^\\s-*\\(\\(signal\\)\\|alias\\)\\>" parse-partial-sexp 0 looking-at "[ \n \f,]+\\([a-zA-Z]\\w*\\)" "[ \n \f]+\\([a-zA-Z]\\w*\\)[^;]*\\<is[ \n \f]+\\([a-zA-Z]\\w*\\)" "^\\s-*\\(\\w+\\s-*:\\s-*\\(block\\|\\(for\\|if\\).*\\<generate\\>\\)\\|\\(end\\)\\s-+block\\)\\>" 4 vhdl-backward-sexp "^\\s-*\\w+\\s-*:\\s-*\\(block\\|generate\\)\\>" "^\\s-*begin\\>" "[ \n,]+\\(\\w+\\)" "[ \n]+\\(\\w+\\)[^;]*\\<is[ \n]+\\(\\w+\\)"] 16 (#$ . 270454)])#@49 Fix all generic/port clauses in current buffer. (defalias 'vhdl-fix-clause-buffer #[0 "\212\302\303 p\304\305#\216\306 !\210eb\210\307\310!\210\311\312\313\302#\2032�\314\225b\210\3151.�\316 0\210\202�\210\202�\307\317!)\266\202*\207" [case-fold-search vhdl-mode-ext-syntax-table t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table message "Fixing generic/port clauses..." re-search-forward "^\\s-*\\(generic\\|port\\)[ \n \f]*(" nil 0 (error) vhdl-fix-clause "Fixing generic/port clauses...done"] 6 (#$ . 273403) nil])#@53 Fix closing parenthesis within generic/port clause. (defalias 'vhdl-fix-clause #[0 "\212\302\303 p\304\305#\216\306 !\210`\307\211\211\210\310\311\307\302#\204&�\312\313!\266\203\202\233�\314\225b\210`S\262\315 \210\316\317!\203I�\314\225Sb\210\320 \262\307u\210\315 \210\2021�\211b\210\321 V\203W�\312\313!\210\212\322 \210\316\323!)\203o�\324 \210\325 \210\320 \262\326c\210b\210\3271}�\330 0\210\202\201�\210db\210`W\203\216�\331\332!\210\202o�`V\205\231�\211b\210\333c\266\203)\266\202*\207" [case-fold-search vhdl-mode-ext-syntax-table t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table nil re-search-backward "^\\s-*\\(generic\\|port\\)[ \n \f]*(" error "ERROR: Not within a generic/port clause" 0 vhdl-forward-syntactic-ws looking-at "\\w+\\([ \n \f]*,[ \n \f]*\\w+\\)*[ \n \f]*:[ \n \f]*\\w+[^;]*;" point-marker line-end-position beginning-of-line "^\\s-*);" vhdl-line-kill vhdl-backward-syntactic-ws ";" (error) forward-sexp delete-char -1 ")"] 9 (#$ . 273986) nil])#@51 Syntax of prompt inserted by template generators. (defconst vhdl-template-prompt-syntax "[^ =<>][^<>@.\n]*[^ =<>]" (#$ . 275037))#@118 Indicates whether a template has been invoked by a hook or by key or menu. Used for undoing after template abortion. (defvar vhdl-template-invoked-by-hook nil (#$ . 275173))#@12 (fn ARG) (defalias 'vhdl-character-to-event #[257 "\300\207" [nil] 2 (#$ . 275352)]) (byte-code "\300\301\302\303!\203\f�\303\202 �\304\"\207" [defalias vhdl-character-to-event fboundp character-to-event identity] 4)#@92 Return the working library name of the current project or "work" if no project is defined. (defalias 'vhdl-work-library #[0 "\303\304\305 \"8\206 �\n!\207" [vhdl-project-alist vhdl-project vhdl-default-library vhdl-resolve-env-variable 6 vhdl-aget] 5 (#$ . 275576)]) (byte-code "\300\301\302\303\304DD\305\306\307\310\311\312\313\314\315& \207" [custom-declare-variable vhdl-electric-mode funcall function #[0 "\300\207" [nil] 1 ""] "Non-nil if Vhdl-Electric mode is enabled.\nSee the `vhdl-electric-mode' command\nfor a description of this minor mode." :set custom-set-minor-mode :initialize custom-initialize-default :type boolean :group vhdl-mode] 12)#@614 Toggle VHDL electric mode. This is a global minor mode. If called interactively, toggle the `Vhdl-Electric mode' mode. If the prefix argument is positive, enable the mode, and if it is zero or negative, disable the mode. If called from Lisp, toggle the mode if ARG is `toggle'. Enable the mode if ARG is nil, omitted, or is a positive number. Disable the mode if ARG is a negative number. To check whether the minor mode is enabled in the current buffer, evaluate `(default-value \='vhdl-electric-mode)'. The mode's hook is called both when the mode is enabled and when it is disabled. (fn &optional ARG) (defalias 'vhdl-electric-mode #[256 "\301 \302\303\304=\203�\305\303!?\202!�\247\203 �\306W\203 �\307\202!�\310\"\210\311\300!\2038�\312\303\"\305\303!\2038�\303B\313\314\305\303!\203D�\315\202E�\316\"\210\317\320!\203n�\321\303!\210\301 \203]�\211\301 \232\203n�\322\323\324\305\303!\203j�\325\202k�\326\327$\210\210\330 \210\305\303!\207" [global-minor-modes current-message set-default vhdl-electric-mode toggle default-value 1 nil t boundp delq run-hooks vhdl-electric-mode-hook vhdl-electric-mode-on-hook vhdl-electric-mode-off-hook called-interactively-p any customize-mark-as-set message "%s %sabled%s" "Vhdl-Electric mode" "en" "dis" "" force-mode-line-update] 7 (#$ . 276238) (byte-code "\203\n�\301!\202 �\302C\207" [current-prefix-arg prefix-numeric-value toggle] 2)]) (defvar vhdl-electric-mode-hook nil) (byte-code "\301\302N\204\f�\303\301\302\304#\210\303\301\305\306#\210\303\301\307\310C#\210\311\312\310\313\300!\205#�\310\211%\210\314\315\316\317\320DD\321\322\323\324\325\326\327\330\331& \207" [vhdl-electric-mode-map vhdl-electric-mode-hook variable-documentation put "Hook run after entering or leaving `vhdl-electric-mode'.\nNo problems result if this variable is not bound.\n`add-hook' automatically binds it. (This is true for all hook variables.)" custom-type hook standard-value nil add-minor-mode vhdl-electric-mode boundp custom-declare-variable vhdl-stutter-mode funcall function #[0 "\300\207" [nil] 1 ""] "Non-nil if Vhdl-Stutter mode is enabled.\nSee the `vhdl-stutter-mode' command\nfor a description of this minor mode." :set custom-set-minor-mode :initialize custom-initialize-default :type boolean :group vhdl-mode] 12)#@614 Toggle VHDL stuttering mode. This is a global minor mode. If called interactively, toggle the `Vhdl-Stutter mode' mode. If the prefix argument is positive, enable the mode, and if it is zero or negative, disable the mode. If called from Lisp, toggle the mode if ARG is `toggle'. Enable the mode if ARG is nil, omitted, or is a positive number. Disable the mode if ARG is a negative number. To check whether the minor mode is enabled in the current buffer, evaluate `(default-value \='vhdl-stutter-mode)'. The mode's hook is called both when the mode is enabled and when it is disabled. (fn &optional ARG) (defalias 'vhdl-stutter-mode #[256 "\301 \302\303\304=\203�\305\303!?\202!�\247\203 �\306W\203 �\307\202!�\310\"\210\311\300!\2038�\312\303\"\305\303!\2038�\303B\313\314\305\303!\203D�\315\202E�\316\"\210\317\320!\203n�\321\303!\210\301 \203]�\211\301 \232\203n�\322\323\324\305\303!\203j�\325\202k�\326\327$\210\210\330 \210\305\303!\207" [global-minor-modes current-message set-default vhdl-stutter-mode toggle default-value 1 nil t boundp delq run-hooks vhdl-stutter-mode-hook vhdl-stutter-mode-on-hook vhdl-stutter-mode-off-hook called-interactively-p any customize-mark-as-set message "%s %sabled%s" "Vhdl-Stutter mode" "en" "dis" "" force-mode-line-update] 7 (#$ . 278527) (byte-code "\203\n�\301!\202 �\302C\207" [current-prefix-arg prefix-numeric-value toggle] 2)]) (defvar vhdl-stutter-mode-hook nil) (byte-code "\301\302N\204\f�\303\301\302\304#\210\303\301\305\306#\210\303\301\307\310C#\210\311\312\310\313\300!\205#�\310\211%\207" [vhdl-stutter-mode-map vhdl-stutter-mode-hook variable-documentation put "Hook run after entering or leaving `vhdl-stutter-mode'.\nNo problems result if this variable is not bound.\n`add-hook' automatically binds it. (This is true for all hook variables.)" custom-type hook standard-value nil add-minor-mode vhdl-stutter-mode boundp] 6)#@94 -- starts a comment, --- draws a horizontal line, ---- starts a display comment. (fn COUNT) (defalias 'vhdl-electric-dash #[257 "\203]�\304 \204]� \203� `U\203�\305\nb\210\306\305!\210\307 \207h\310U\204)�\311!\207\311!\210\312\313!\210\314 \211\310U\203T�\315 \210\312\316!\210\314 \211\310U\203L�\307\317!\207\320! B\211\207\320! B\321 \207\311!\207" [vhdl-stutter-mode abbrev-start-location last-abbrev-location unread-command-events vhdl-in-literal nil beginning-of-line vhdl-comment-display 45 self-insert-command message "Enter `-' for horiz. line, RET for commenting-out code, else enter comment" read-char vhdl-comment-display-line "Enter `-' for display comment, else continue coding" t vhdl-character-to-event vhdl-comment-insert] 5 (#$ . 280438) "p"])#@39 `[' --> `(', `([' --> `[' (fn COUNT) (defalias 'vhdl-electric-open-bracket #[257 "\203#�\211\301U\203#�\302 \204#�h\303U\203�\304\305!\210\306\307\301\"\207\306\303\301\"\207\310!\207" [vhdl-stutter-mode 1 vhdl-in-literal 40 delete-char -1 insert-char 91 self-insert-command] 4 (#$ . 281218) "p"])#@39 `]' --> `)', `)]' --> `]' (fn COUNT) (defalias 'vhdl-electric-close-bracket #[257 "\203)�\211\301U\203)�\302 \204)�h\303U\203!�\304\305!\210\306\307\301\"\210\202&�\306\303\301\"\210\310 \207\311!\207" [vhdl-stutter-mode 1 vhdl-in-literal 41 delete-char -1 insert-char 93 blink-matching-open self-insert-command] 4 (#$ . 281525) "p"])#@26 \='\=' --> " (fn COUNT) (defalias 'vhdl-electric-quote #[257 "\203#�\211\302U\203#�\303 \204#�h U\203�\304\305!\210\306\307\302\"\207\306\310\302\"\207\311!\207" [vhdl-stutter-mode vhdl-last-input-event 1 vhdl-in-literal delete-char -1 insert-char 34 39 self-insert-command] 4 (#$ . 281868) "p"])#@46 `;;' --> ` : ', `: ;' --> ` := ' (fn COUNT) (defalias 'vhdl-electric-semicolon #[257 "\203A�\211\304U\203A�\305 \204A�h U\203)�\306\307!\210h\310=\204\"�\311c\210\312c\210\313\211\207 \313=\203<�h\310U\203<�\306\307!\210\314c\207\315\316\304\"\207\317!\207" [vhdl-stutter-mode vhdl-last-input-event this-command last-command 1 vhdl-in-literal delete-char -1 32 " " ": " vhdl-electric-colon "= " insert-char 59 self-insert-command] 4 (#$ . 282174) "p"])#@29 `,,' --> ` <= ' (fn COUNT) (defalias 'vhdl-electric-comma #[257 "\203*�\211\302U\203*�\303 \204*�h U\203%�\304\305!\210h\306=\204\"�\307c\210\310c\207\311\312\302\"\207\313!\207" [vhdl-stutter-mode vhdl-last-input-event 1 vhdl-in-literal delete-char -1 32 " " "<= " insert-char 44 self-insert-command] 4 (#$ . 282636) "p"])#@29 `..' --> ` => ' (fn COUNT) (defalias 'vhdl-electric-period #[257 "\203-�\211\301U\203-�\302 \204-�h\303 \304H=\203(�\305\306!\210h\307=\204%�\310c\210\311c\207\312\313\301\"\207\314!\207" [vhdl-stutter-mode 1 vhdl-in-literal this-command-keys 0 delete-char -1 32 " " "=> " insert-char 46 self-insert-command] 4 (#$ . 282968) "p"])#@29 `==' --> ` == ' (fn COUNT) (defalias 'vhdl-electric-equal #[257 "\203*�\211\302U\203*�\303 \204*�h U\203%�\304\305!\210h\306=\204\"�\307c\210\310c\207\311\312\302\"\207\313!\207" [vhdl-stutter-mode vhdl-last-input-event 1 vhdl-in-literal delete-char -1 32 " " "== " insert-char 61 self-insert-command] 4 (#$ . 283307) "p"])#@65 Insert a pair of round parentheses, placing point between them. (defalias 'vhdl-template-paired-parens #[0 "\300c\210\301u\207" ["()" -1] 1 (#$ . 283639) nil])#@27 Insert alias declaration. (defalias 'vhdl-template-alias #[0 "`\300\301!\210\302\303\304\305`%\2052�\306c\210\302\307\310\311!\205�\312\313Q\304\305#\204'�\314\315!\210\300\316!\210\302\303\317\"\210\320 \207" [vhdl-insert-keyword "ALIAS " vhdl-template-field "name" nil t " : " "[type" vhdl-standard-p ams " or nature" "]" delete-char -3 " IS " ";" vhdl-comment-insert-inline] 7 (#$ . 283804) nil])#@22 Insert architecture. (defalias 'vhdl-template-architecture #[0 "\303 `\304\305\306!\210\307\310\304\311`%\211\262\205T�\305\312!\210\212\311\313 p\314\315#\216\316 !\210\317\320\304\311#)\266\202*\203=�\321\322!c\210\202A�\307\323!\210\305\324!\210\325\326\327!?\205N�\330\n\331>$\207" [case-fold-search vhdl-mode-ext-syntax-table vhdl-insert-empty-lines current-indentation nil vhdl-insert-keyword "ARCHITECTURE " vhdl-template-field "name" t " OF " syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table vhdl-re-search-backward "\\<entity \\(\\w+\\) is\\>" match-string 1 "entity name" " IS\n" vhdl-template-begin-end vhdl-standard-p 87 "ARCHITECTURE" (unit all)] 9 (#$ . 284211) nil])#@62 Insert array type definition. (fn KIND &optional SECONDARY) (defalias 'vhdl-template-array #[513 "`\300\301!\210\302\303\304?`%\204�\205)�\300\305!\210\302\306=\203#�\307\202$�\310!\210\300\311!\207" [vhdl-insert-keyword "ARRAY (" vhdl-template-field "range" nil ") OF " type "type" "nature" ";"] 9 (#$ . 284958) nil])#@32 Insert an assertion statement. (defalias 'vhdl-template-assert #[0 "`\301\302!\210\203\f�\303c\210\304\305\306\307`%\205I�\203�\310c\210`\262\301\311!\210\304\312\306\211\211\211\307&\2044�\211`|\210`\262\301\313!\210\304\314\306\307#\204G�\211`|\210\315c\207" [vhdl-conditions-in-parenthesis vhdl-insert-keyword "ASSERT " "(" vhdl-template-field "condition (negated)" nil t ")" " REPORT " "string expression" " SEVERITY " "[NOTE | WARNING | ERROR | FAILURE]" ";"] 8 (#$ . 285288) nil])#@51 Insert an attribute declaration or specification. (defalias 'vhdl-template-attribute #[0 "\300\301\302\303#\304=\203 �\305 \207\306 \207" [vhdl-decision-query "attribute" "(d)eclaration or (s)pecification?" t 115 vhdl-template-attribute-spec vhdl-template-attribute-decl] 4 (#$ . 285787) nil])#@34 Insert an attribute declaration. (defalias 'vhdl-template-attribute-decl #[0 "`\300\301!\210\302\303\304\305`%\205�\302\306\307\"\210\310 \207" [vhdl-insert-keyword "ATTRIBUTE " vhdl-template-field "name" " : " t "type" ";" vhdl-comment-insert-inline] 7 (#$ . 286086) nil])#@36 Insert an attribute specification. (defalias 'vhdl-template-attribute-spec #[0 "`\300\301!\210\302\303\304\305`%\205$�\300\306!\210\302\307\310\"\210\302\311!\210\300\312!\210\302\313\314\"\207" [vhdl-insert-keyword "ATTRIBUTE " vhdl-template-field "name" nil t " OF " "entity names | OTHERS | ALL" " : " "entity class" " IS " "expression" ";"] 7 (#$ . 286367) nil])#@17 Insert a block. (defalias 'vhdl-template-block #[0 "\300 `\301\302\303!\210b\210\304\305\301\306`\307\\%\211\262\205K�\310\311!\210\311u\210\312c\210\304\313\301\306#\2032�\314c\210\2026�\315\316!\210\317\320!\204@�\302\321!\210\322c\210\323\324#\210\325 \207" [current-indentation nil vhdl-insert-keyword ": BLOCK " vhdl-template-field "label" t 8 forward-word-strictly 1 "(" "[guard expression]" ")" delete-char -2 vhdl-standard-p 87 " IS" "\n" vhdl-template-begin-end "BLOCK" vhdl-comment-block] 10 (#$ . 286740) nil])#@41 Insert a block configuration statement. (defalias 'vhdl-template-block-configuration #[0 "\301 `\302\303!\210\304\305\306\307`%\205#�\302\310!\210j\210\302\311!\210\312\210\\j\207" [vhdl-basic-offset current-indentation vhdl-insert-keyword "FOR " vhdl-template-field "block name" nil t "\n\n" "END FOR;" 0] 8 (#$ . 287272) nil])#@27 Insert a break statement. (defalias 'vhdl-template-break #[0 "\301\302\303!\210`\262\304c\210\302\305!\210\306\307\310\311#\203�\306\312\313\"\210\202/�`\314\315!\210`|\210\306\307\313\311#\203<�\306\316!\210`\262\317c\210\202 �\211`|\210\320 \204[�\302\321!\210\306\322\301\311#\203W�`\262\202[�\211`|\210\302\323!\210\203f�\324c\210\306\325\301\311#\203x�\203|�\326c\210\202|�\211`|\210\327c\207" [vhdl-conditions-in-parenthesis nil vhdl-insert-keyword "BREAK" " " "FOR " vhdl-template-field "[quantity name]" " USE " t "quantity name" " => " forward-word-strictly -1 "expression" ", " vhdl-sequential-statement-p " ON " "[sensitivity list]" " WHEN " "(" "[condition]" ")" ";"] 5 (#$ . 287611) nil])#@47 Insert a case statement. (fn &optional KIND) (defalias 'vhdl-template-case #[256 "\302 `\303\204�\304 \204�\305\306!\204�\307\202�\310\262\311=\203&�\305\312!\203-�\313\314!\210\202J�\313\315!\210b\210\316\317\303\320#\262\211\204C�\321\322!\210\323\324!\210\324u\210\316\325\303\320`%\205\225�\313\326\307=\203`�\327\202a�\330\331Q!\210j\210\313\332!\210\211\203u�\326\261\210\333c\210\334y\210 \\j\210\313\335!\210`\336c\210 \\j\210\313\337!\210\211b\262\207" [vhdl-optional-labels vhdl-basic-offset current-indentation nil vhdl-sequential-statement-p vhdl-standard-p ams is use all 87 vhdl-insert-keyword "CASE " ": CASE " vhdl-template-field "[label]" t delete-char 2 forward-word-strictly 1 "expression" " " "IS" "USE" "\n\n" "END CASE" ";" -1 "WHEN " " => ;\n" "WHEN OTHERS => null;"] 10 (#$ . 288324) nil])#@37 Insert a sequential case statement. (defalias 'vhdl-template-case-is #[0 "\300\301!\207" [vhdl-template-case is] 2 (#$ . 289161) nil])#@39 Insert a simultaneous case statement. (defalias 'vhdl-template-case-use #[0 "\300\301!\207" [vhdl-template-case use] 2 (#$ . 289301) nil])#@33 Insert a component declaration. (defalias 'vhdl-template-component #[0 "\300 \207" [vhdl-template-component-decl] 1 (#$ . 289445) nil])#@111 Insert a component configuration (uses `vhdl-template-configuration-spec' since these are almost equivalent). (defalias 'vhdl-template-component-conf #[0 "\300 \301\302!\211\205�\303c\210j\210\304\305!\210\211\306=\205�\307\207" [current-indentation vhdl-template-configuration-spec t "\n" vhdl-insert-keyword "END FOR;" no-use 0] 4 (#$ . 289587) nil])#@33 Insert a component declaration. (defalias 'vhdl-template-component-decl #[0 "\301 `\302\211\303\304!\210\305\306\302\307`%\211\262\205[�\310\311!\204!�\303\312!\210\313c\210j\210\303\314!\210\310\311!\2046�\315\261\210\316c\210i\262\317\210\\j\210\320\307\211\"\210\321c\210\\j\210\322\307!\210\323\324!\210\211u\207" [vhdl-basic-offset current-indentation nil vhdl-insert-keyword "COMPONENT " vhdl-template-field "name" t vhdl-standard-p 87 " IS" "\n\n" "END COMPONENT" " " ";" 0 vhdl-template-generic-list "\n" vhdl-template-port-list beginning-of-line 2] 10 (#$ . 289949) nil])#@45 Insert a component instantiation statement. (defalias 'vhdl-template-component-inst #[0 "\301 `\302\211\303\304\302\305`%\205\255�\306c\210\307 \204�\303\310!\210\202t�\303\311\312\305#\262\206+�\313\226\262\314\267\202p�`\303\315\316\305`\302\317 &\210\303\320\321\"\210\303\322\302\305#\203U�\323c\266\202t�\324\325!\266\202t�\303\315\316\302\211\211\211\317 &\210\303\326!\210\202t�\303\310!\210\327c\210\\j\210`\262\330\331!\210\332\305\211#\203\223�\327c\210\\j\210`\262\330\333!\210\332\305\211#\204\253�\334 `|\210\324\325!\210\335c\207" [vhdl-basic-offset current-indentation nil vhdl-template-field "instance label" t ": " vhdl-use-direct-instantiation "component name" "[COMPONENT | ENTITY | CONFIGURATION]" " " "" #s(hash-table size 2 test equal rehash-size 1.5 rehash-threshold 0.8125 purecopy t data ("ENTITY" 52 "CONFIGURATION" 93)) "library name" "." vhdl-work-library "entity name" "(" "[architecture name]" ")" delete-char -1 "configuration name" "\n" vhdl-insert-keyword "GENERIC " vhdl-template-map "PORT " line-beginning-position ";"] 13 (#$ . 290547) nil])#@41 Insert a conditional signal assignment. (defalias 'vhdl-template-conditional-signal-asst #[0 "\302\303!\205e�\304c\210i`\305\302\306!\210`\262\307\310!\210\203�\311c\210\302\312\305\313#\203S�\203-�\314c\210`\262\307\315!\210\316c\210j\210\302\317\305\313#\203S�`\262\307\310!\210\203�\311c\210\202�\211`|\210\320c\210 \205c�\321`\322#\266\203\207" [vhdl-conditions-in-parenthesis vhdl-auto-align vhdl-template-field "target signal" " <= " nil "waveform" vhdl-insert-keyword " WHEN " "(" "[condition]" t ")" " ELSE" "\n" "[waveform]" ";" vhdl-align-region-groups 1] 7 (#$ . 291650) nil])#@196 Insert a configuration specification if within an architecture, a block or component configuration if within a configuration declaration, a configuration declaration if not within a design unit. (defalias 'vhdl-template-configuration #[0 "\302\303 p\304\305#\216\306 !\210\212\307\310\311\302#)\203'�\312\313!\226\314\232\203'�\315 \202P�\212\307\316\311\302#)\203N�\312\313!\226\317\232\203N�\320\321\322\302#\323=\203I�\324 \202P�\325 \202P�\326 )\266\202)\207" [case-fold-search vhdl-mode-ext-syntax-table t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table re-search-backward "^\\(architecture\\|end\\)\\>" nil match-string 1 "ARCHITECTURE" vhdl-template-configuration-spec "^\\(configuration\\|end\\)\\>" "CONFIGURATION" vhdl-decision-query "configuration" "(b)lock or (c)omponent configuration?" 99 vhdl-template-component-conf vhdl-template-block-configuration vhdl-template-configuration-decl] 6 (#$ . 292255) nil])#@68 Insert a configuration specification. (fn &optional OPTIONAL-USE) (defalias 'vhdl-template-configuration-spec #[256 "\301 `\302\211\303\304!\210\305\306\307\310`%\205\316�\305\311\312\"\210\\j\210`\262\303\313!\210\203:�\305\314\315\310#\211\262\204:�`|\210\316\207\204D�\305\317\315\"\262\206I�\320\226\262\321\267\202\306�\305\322\323\302\211\211\211\324 &\210\305\325\326\"\210\305\327\302\310#\203q�\330c\210\202u�\331\332!\210\312c\210\333_\\j\210`\262\303\334!\210\335\310\211#\203\230�\312c\210\333_\\j\210`\262\303\336!\210\335\310\211#\204\260�\337 `|\210\331\332!\210\340c\210\310\207\305\322\323\302\211\211\211\324 &\210\305\341\340\"\207\331\332!\210\340c\210\310\207" [vhdl-basic-offset current-indentation nil vhdl-insert-keyword "FOR " vhdl-template-field "instance names | OTHERS | ALL" " : " t "component name" "\n" "USE " "[ENTITY | CONFIGURATION | OPEN]" " " no-use "ENTITY | CONFIGURATION | OPEN" "" #s(hash-table size 2 test equal rehash-size 1.5 rehash-threshold 0.8125 purecopy t data ("ENTITY" 82 "CONFIGURATION" 181)) "library name" "." vhdl-work-library "entity name" "(" "[architecture name]" ")" delete-char -1 2 "GENERIC " vhdl-template-map "PORT " line-beginning-position ";" "configuration name"] 13 (#$ . 293239) nil])#@37 Insert a configuration declaration. (defalias 'vhdl-template-configuration-decl #[0 "\304 `\305\211\211\211\306\307!\210\310\311\305\312`%\211\262\205\211�\306\313!\210\212\312\314 p\315\316#\216\317 !\210\320\321\305\312#\262\322\323!+\262\266\203L�\324\232\204L�c\210\202P�\310\325!\210\306\326!\210\n\327>\203]�\330c\210 \\j\210`\262\330c\210\n\331>\203q�\330c\210j\210\306\332!\210\333\334!\204\202�\306\307!\210\335\261\210\211b\207" [case-fold-search vhdl-mode-ext-syntax-table vhdl-insert-empty-lines vhdl-basic-offset current-indentation nil vhdl-insert-keyword "CONFIGURATION " vhdl-template-field "name" t " OF " syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table vhdl-re-search-backward "\\<entity \\(\\w*\\) is\\>" match-string 1 "" "entity name" " IS\n" (unit all) "\n" (unit all) "END " vhdl-standard-p 87 ";"] 12 (#$ . 294520) nil])#@32 Insert a constant declaration. (defalias 'vhdl-template-constant #[0 "`\300 \301\302!\210\303\304\305\306`%\205A�\307c\210\211\203�\301\310!\210\303\311!\210\211\203*�\312c\210\313 \207`\314c\210\303\315\305\306#\204:�\211`|\210\312c\210\313 \262\207" [vhdl-in-argument-list-p vhdl-insert-keyword "CONSTANT " vhdl-template-field "name" nil t " : " "IN " "type" ";" vhdl-comment-insert-inline " := " "[initialization]"] 8 (#$ . 295441) nil])#@31 Insert a context declaration. (defalias 'vhdl-template-context #[0 "\302 `\303\211\304\305!\210\306\307\303\310`%\211\262\205P�\304\311!\210\312>\203$�\313c\210 \\j\210`\262\313c\210\314>\2038�\313c\210j\210\304\315!\210\316\317!\204I�\304\305!\210\320\261\210\211b\207" [vhdl-insert-empty-lines vhdl-basic-offset current-indentation nil vhdl-insert-keyword "CONTEXT " vhdl-template-field "name" t " IS\n" (unit all) "\n" (unit all) "END " vhdl-standard-p 87 ";"] 10 (#$ . 295890) nil])#@17 Insert nothing. (defalias 'vhdl-template-default #[0 "\300c\210\301 \210\302\303!\210\304\303!\210\303u\207" [" " unexpand-abbrev backward-word-strictly 1 vhdl-case-word] 2 (#$ . 296392) nil])#@28 Insert nothing and indent. (defalias 'vhdl-template-default-indent #[0 "\300c\210\301 \210\302\303!\210\304\303!\210\303u\210\305 \207" [" " unexpand-abbrev backward-word-strictly 1 vhdl-case-word indent-according-to-mode] 2 (#$ . 296590) nil])#@32 Insert a disconnect statement. (defalias 'vhdl-template-disconnect #[0 "`\300\301!\210\302\303\304\305`%\205�\302\306!\210\300\307!\210\302\310\311\"\207" [vhdl-insert-keyword "DISCONNECT " vhdl-template-field "signal names | OTHERS | ALL" " : " t "type" " AFTER " "time expression" ";"] 7 (#$ . 296840) nil])#@27 Insert an else statement. (defalias 'vhdl-template-else #[0 "\303\304\305 p\306\307#\216\310 !\210\311\312!\210\212\313\314\303\304#)\203)�\315\316!\203)�\317c\202@�\320 \2042�\311\321!\210\322 \210\323 \262\324c\210\n\\j)\266\202)\207" [case-fold-search vhdl-mode-ext-syntax-table vhdl-basic-offset nil t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table vhdl-insert-keyword "ELSE" vhdl-re-search-backward "\\(\\(\\<when\\>\\)\\|;\\)" match-string 2 " " vhdl-sequential-statement-p " GENERATE" indent-according-to-mode current-indentation "\n"] 7 (#$ . 297157) nil])#@28 Insert an elsif statement. (defalias 'vhdl-template-elsif #[0 "`\302\303\304!\210\203 �\305c\210\306\307\302\310`%\205C�\203�\311c\210\312 \210\313 \262\303\314\315 \2030�\316\202;�\317\320!\203:�\321\202;�\322\323Q!\210\211 \\j\207" [vhdl-conditions-in-parenthesis vhdl-basic-offset nil vhdl-insert-keyword "ELSIF " "(" vhdl-template-field "condition" t ")" indent-according-to-mode current-indentation " " vhdl-sequential-statement-p "THEN" vhdl-standard-p ams "USE" "GENERATE" "\n"] 8 (#$ . 297787) nil])#@19 Insert an entity. (defalias 'vhdl-template-entity #[0 "\302 `\303\211\304\305!\210\306\307\303\310`%\211\262\205v�\304\311!\210j\210\304\312!\210\313\314!\204,�\304\305!\210\315\261\210i\262\316\210\\j\210 \317>\203E�\320c\210\\j\210\321\310!\203Y� \322>\203Y�\320c\210\320c\210\\j\210\323\310!\203p� \324>\203p�\320c\210\325\326!\210\211u\207" [vhdl-basic-offset vhdl-insert-empty-lines current-indentation nil vhdl-insert-keyword "ENTITY " vhdl-template-field "name" t " IS\n\n" "END " vhdl-standard-p 87 ";" 0 (unit all) "\n" vhdl-template-generic-list (unit all) vhdl-template-port-list (unit all) beginning-of-line 2] 10 (#$ . 298305) nil])#@27 Insert an exit statement. (defalias 'vhdl-template-exit #[0 "`\301\302!\210\303\304\305\306`%\2036�`\301\307!\210\203�\310c\210\303\311\305\306#\203.�\2032�\312c\266\202:�\211`|\210\210\202:�\313\314!\210\315c\207" [vhdl-conditions-in-parenthesis vhdl-insert-keyword "EXIT " vhdl-template-field "[loop label]" nil t " WHEN " "(" "[condition]" ")" delete-char -1 ";"] 7 (#$ . 298970) nil])#@28 Insert a file declaration. (defalias 'vhdl-template-file #[0 "`\300\301!\210\302\303\304\305`%\205K�\306c\210\302\307!\210\310\311!\204,�\300\312!\210\302\313\304\305#\204,�\314\315!\210\300\316!\210\310\311!\203<�\302\317\320\305#\210\302\321\304\211\211\211\305&\210\322c\210\323 \207" [vhdl-insert-keyword "FILE " vhdl-template-field "name" nil t " : " "type" vhdl-standard-p 87 " OPEN " "[READ_MODE | WRITE_MODE | APPEND_MODE]" delete-char -6 " IS " "[IN | OUT]" " " "filename-string" ";" vhdl-comment-insert-inline] 8 (#$ . 299369) nil])#@290 Insert a block or component configuration if within a configuration declaration, a configuration specification if within an architecture declarative part (and not within a subprogram), a for-loop if within a sequential statement part (subprogram or process), and a for-generate otherwise. (defalias 'vhdl-template-for #[0 "\302\303 p\304\305#\216\306 !\210\307 \203�\310 \202Z�\212\311\312\313\302#)\203@�\314\315!\226\316\232\203@�\317\320\321\302#\322=\203;�\323 \202Z�\324 \202Z�\212\311\325\313\302#)\203X�\314\315!\226\326\232\203X�\327 \202Z�\330 )\266\202)\207" [case-fold-search vhdl-mode-ext-syntax-table t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table vhdl-sequential-statement-p vhdl-template-for-loop re-search-backward "^\\(configuration\\|end\\)\\>" nil match-string 1 "CONFIGURATION" vhdl-decision-query "for" "(b)lock or (c)omponent configuration?" 99 vhdl-template-component-conf vhdl-template-block-configuration "^\\(architecture\\|entity\\|begin\\|end\\)\\>" "ARCHITECTURE" vhdl-template-configuration-spec vhdl-template-for-generate] 6 (#$ . 299920) nil])#@24 Insert a for-generate. (defalias 'vhdl-template-for-generate #[0 "\300 `\301\211\302\303!\210\304 \262b\210\305\306\301\307%\211\262\2051�\211b\210\305\310!\210\302\311!\210\305\312!\210\313\"\207" [current-indentation nil vhdl-insert-keyword ": FOR " point-marker vhdl-template-field "label" t "loop variable" " IN " "range" vhdl-template-generate-body] 10 (#$ . 301062) nil])#@20 Insert a for loop. (defalias 'vhdl-template-for-loop #[0 "\303 `\304\211\305=\204�\306\307!\210\202/�\306\310!\210b\210\311\312\304\313#\262\204(�\314\315!\210\316\317!\210\317u\210\311\320\304\313`%\211\262\205p�\306\321!\210\311\322!\210\306\323!\210j\210\306\324!\210\203]�\325\326\261\210\202i�\326c\210 \203i�\327\261\210\330y\210\n\\j\207" [vhdl-optional-labels vhdl-self-insert-comments vhdl-basic-offset current-indentation nil all vhdl-insert-keyword "FOR " ": FOR " vhdl-template-field "[label]" t delete-char 2 forward-word-strictly 1 "loop variable" " IN " "range" " LOOP\n\n" "END LOOP" " " ";" " -- " -1] 10 (#$ . 301453) nil])#@61 Insert a function declaration or body. (fn &optional KIND) (defalias 'vhdl-template-function #[256 "\302 `\303\304\305!\210\306\307\303\310`%\211\262\205_�\311\310!\210\203#�\312`\313#\210\303\210\314c\210 \\j\210\304\315!\210\306\316!\210\203@�\317=\202F�\320\303\321\"\322=\203]�\304\323!\210\324\325\326!?\205V�\327#\210\330 \207\331c\207" [vhdl-auto-align vhdl-basic-offset current-indentation nil vhdl-insert-keyword "FUNCTION " vhdl-template-field "name" t vhdl-template-argument-list vhdl-align-region-groups 1 "\n" "RETURN " "type" body vhdl-decision-query "(d)eclaration or (b)ody?" 98 " IS\n" vhdl-template-begin-end vhdl-standard-p 87 "FUNCTION" vhdl-comment-block ";"] 10 (#$ . 302116) nil])#@32 Insert a function declaration. (defalias 'vhdl-template-function-decl #[0 "\300\301!\207" [vhdl-template-function decl] 2 (#$ . 302836) nil])#@32 Insert a function declaration. (defalias 'vhdl-template-function-body #[0 "\300\301!\207" [vhdl-template-function body] 2 (#$ . 302983) nil])#@29 Insert a generation scheme. (defalias 'vhdl-template-generate #[0 "\300\301\302\303#\304=\203 �\305 \207\306 \207" [vhdl-decision-query nil "(f)or or (i)f?" t 105 vhdl-template-if-generate vhdl-template-for-generate] 4 (#$ . 303130) nil])#@73 Insert generic declaration, or generic map in instantiation statements. (defalias 'vhdl-template-generic #[0 "`\302\303 p\304\305#\216\306 !\210\212\307\310\311\302#)\203)�\312\313!\226\314\232\203)�\315\311!\202M�\212\316 \2062�\317\320!)\204?�\321 @@\322=\203I�\323\324!\210\325!\202M�\315\311\302\")\266\202)\207" [case-fold-search vhdl-mode-ext-syntax-table t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table re-search-backward "^\\(entity\\|end\\)\\>" nil match-string 1 "ENTITY" vhdl-template-generic-list beginning-of-line looking-at "^\\s-*\\w+\\s-*:\\s-*\\w+" vhdl-get-syntactic-context statement-cont vhdl-insert-keyword "GENERIC " vhdl-template-map] 7 (#$ . 303374) nil])#@45 Insert group or group template declaration. (defalias 'vhdl-template-group #[0 "\300\301\302\303#\304=\203 �\305 \207\306 \207" [vhdl-decision-query "group" "(d)eclaration or (t)emplate declaration?" t 116 vhdl-template-group-template vhdl-template-group-decl] 4 (#$ . 304119) nil])#@27 Insert group declaration. (defalias 'vhdl-template-group-decl #[0 "`\300\301!\210\302\303\304\305`%\205�\302\306\307\"\210\302\310\311\"\210\312 \207" [vhdl-insert-keyword "GROUP " vhdl-template-field "name" " : " t "template name" " (" "constituent list" ");" vhdl-comment-insert-inline] 7 (#$ . 304407) nil])#@36 Insert group template declaration. (defalias 'vhdl-template-group-template #[0 "`\300\301!\210\302\303\304\305`%\205�\300\306!\210\302\307\310\"\210\311 \207" [vhdl-insert-keyword "GROUP " vhdl-template-field "template name" nil t " IS (" "entity class list" ");" vhdl-comment-insert-inline] 7 (#$ . 304725) nil])#@63 Insert a sequential if statement or an if-generate statement. (defalias 'vhdl-template-if #[0 "\300 \203�\301 \207\302\303!\203�\304\305\306\307#\310=\203�\311 \207\312 \207" [vhdl-sequential-statement-p vhdl-template-if-then vhdl-standard-p ams vhdl-decision-query "if" "(g)enerate or (u)se?" t 117 vhdl-template-if-use vhdl-template-if-generate] 4 (#$ . 305046) nil])#@24 Insert an if-generate. (defalias 'vhdl-template-if-generate #[0 "\301 `\302\211\303\304!\210\305 \262b\210\306\307\302\310%\211\262\2057�\211b\210\203(�\311c\210\306\312!\210\2033�\313c\210\314\"\207" [vhdl-conditions-in-parenthesis current-indentation nil vhdl-insert-keyword ": IF " point-marker vhdl-template-field "label" t "(" "condition" ")" vhdl-template-generate-body] 10 (#$ . 305424) nil])#@46 Insert a sequential if statement. (fn KIND) (defalias 'vhdl-template-if-then-use #[257 "\303 `\304\305=\203�\306\307!\203�\310\311!\210\2024�\310\312!\210b\210\313\314\304\315#\262\211\204-�\316\317!\210\320\321!\210\321u\210 \203;�\322c\210\313\323\304\315`%\205\203� \203L�\324c\210\310\325\326=\203X�\327\202Y�\330\331Q!\210j\210\310\332\326=\203l�\333\202m�\330P!\210\211\203y�\325\261\210\334c\210\335y\210\n\\j\207" [vhdl-optional-labels vhdl-conditions-in-parenthesis vhdl-basic-offset current-indentation nil all vhdl-standard-p 87 vhdl-insert-keyword "IF " ": IF " vhdl-template-field "[label]" t delete-char 2 forward-word-strictly 1 "(" "condition" ")" " " then "THEN" "USE" "\n\n" "END " "IF" ";" -1] 10 (#$ . 305839) nil])#@35 Insert a sequential if statement. (defalias 'vhdl-template-if-then #[0 "\300\301!\207" [vhdl-template-if-then-use then] 2 (#$ . 306593) nil])#@37 Insert a simultaneous if statement. (defalias 'vhdl-template-if-use #[0 "\300\301!\207" [vhdl-template-if-then-use use] 2 (#$ . 306740) nil])#@45 Insert a component instantiation statement. (defalias 'vhdl-template-instance #[0 "\300 \207" [vhdl-template-component-inst] 1 (#$ . 306887) nil])#@33 Insert a library specification. (defalias 'vhdl-template-library #[0 "\300 `\301\211\302\303!\210\304\305\301\306`%\211\262\205G�\307c\210\310\311\"?\205G�`\262\312c\210j\210\302\313!\210c\210\302\314!\210\315u\210\304\316!\203B�\317u\207\211`\317\\|\207" [current-indentation nil vhdl-insert-keyword "LIBRARY " vhdl-template-field "names" t ";" string-match "," "\n" "USE " "..ALL;" -5 "package name" 5] 10 (#$ . 307039) nil])#@17 Insert a limit. (defalias 'vhdl-template-limit #[0 "`\300\301!\210\302\303\304\305`%\205�\302\306!\210\300\307!\210\302\310\311\"\207" [vhdl-insert-keyword "LIMIT " vhdl-template-field "quantity names | OTHERS | ALL" " : " t "type" " WITH " "real expression" ";"] 7 (#$ . 307479) nil])#@16 Insert a loop. (defalias 'vhdl-template-loop #[0 "\300\301\302\303#\211\304\267\202�\305 \207\306 \207\307 \207" [vhdl-decision-query nil "(w)hile, (f)or, or (b)are?" t #s(hash-table size 2 test eq rehash-size 1.5 rehash-threshold 0.8125 purecopy t data (119 11 102 14)) vhdl-template-while-loop vhdl-template-for-loop vhdl-template-bare-loop] 4 (#$ . 307772) nil])#@16 Insert a loop. (defalias 'vhdl-template-bare-loop #[0 "\302 `\303\304=\204�\305\306!\210\202/�\305\307!\210b\210\310\311\303\312#\262\211\204'�\313\314!\210\315\316!\210\313\316!\210\317c\210j\210\305\320!\210\211\203D�\321\322Q\202E�\322c\210\323y\210 \\j\207" [vhdl-optional-labels vhdl-basic-offset current-indentation nil all vhdl-insert-keyword "LOOP " ": LOOP " vhdl-template-field "[label]" t delete-char 2 forward-word-strictly 1 "\n\n" "END LOOP" " " ";" -1] 7 (#$ . 308144) nil])#@92 Insert a map specification with association list. (fn &optional START OPTIONAL SECONDARY) (defalias 'vhdl-template-map #[768 "\206�`\304\211\305\306!\210\204C�\307\205�\310\311\205�\312Q\313?\206&�?\205.�`%\2035�\314\207\203A�\203A�`|\210\304\207 \203M�i\262\202Y�\315 \n\\\262\316c\210j\210\307\205_�\310\317\205f�\312Q\320?\206p�?\205x�`%\203\273�\307\321\322\"\210`\262\316c\210j\210\307\323\320\314#\203\244�\307\321\322\"\210`\262\316c\210j\210\202\213�\211`|\210\324\325!\210\313c\210 \203\271�\326`\327#\210\314\207\203\307�\203\307�`|\210\304\207" [vhdl-association-list-with-formals vhdl-argument-list-indent vhdl-basic-offset vhdl-auto-align nil vhdl-insert-keyword "MAP (" vhdl-template-field "[" "association list" "]" ")" t current-indentation "\n" "formal" " => " "actual" "," "[formal]" delete-char -1 vhdl-align-region-groups 1] 12 (#$ . 308646) nil])#@54 Actualize modification date. (fn &optional NOERROR) (defalias 'vhdl-template-modify #[256 "\303\304 p\305\306#\216\307 !\210\212eb\210\310\n\311\303#\203'�`\311\210`|\210\312 \2020�?\2050�\313\314\n\"*\266\202)\207" [case-fold-search vhdl-mode-ext-syntax-table vhdl-modify-date-prefix-string t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table re-search-forward nil vhdl-template-insert-date error "ERROR: Modification date prefix string \"%s\" not found"] 7 (#$ . 309561) nil])#@51 Call `vhdl-template-modify' with NOERROR non-nil. (defalias 'vhdl-template-modify-noerror #[0 "\300\301!\207" [vhdl-template-modify t] 2 (#$ . 310104)])#@30 Insert a nature declaration. (defalias 'vhdl-template-nature #[0 "`\300\211\211\301\302!\210\303\304\300\305`%\211\262\205\200�\301\306!\210\303\307!\206!�\310\226\211\311\267\202S�\312c\210\202g�`\313\314!\210`|\210\315\316\305\"\210\202g�\317 \262`\313\314!\210`|\210\320\316\305#\210\202g�\301\321!\210\303\322!\210\301\323!\210\303\324!\210\301\325!\210\203u�\317 \262b\210\300\210\326 \210\205~�b\262\207" [nil vhdl-insert-keyword "NATURE " vhdl-template-field "name" t " IS " "across type | ARRAY | RECORD" #1="" #s(hash-table size 3 test equal rehash-size 1.5 rehash-threshold 0.8125 purecopy t data (#1# 40 "ARRAY" 46 "RECORD" 62)) ";" forward-word-strictly -1 vhdl-template-array nature point-marker vhdl-template-record " ACROSS " "through type" " THROUGH " "reference name" " REFERENCE;" vhdl-comment-insert-inline] 10 (#$ . 310262) nil])#@26 Insert a next statement. (defalias 'vhdl-template-next #[0 "`\301\302!\210\303\304\305\306`%\2036�`\301\307!\210\203�\310c\210\303\311\305\306#\203.�\2032�\312c\266\202:�\211`|\210\210\202:�\313\314!\210\315c\207" [vhdl-conditions-in-parenthesis vhdl-insert-keyword "NEXT " vhdl-template-field "[loop label]" nil t " WHEN " "(" "[condition]" ")" delete-char -1 ";"] 7 (#$ . 311129) nil])#@29 Insert an others aggregate. (defalias 'vhdl-template-others #[0 "`h\301U\204 �\204#�\204�\302c\210\303\304!\210\305\306\307\310`%\205&�\311c\207\303\312!\207" [vhdl-template-invoked-by-hook 40 "(" vhdl-insert-keyword "OTHERS => '" vhdl-template-field "value" nil t "')" "OTHERS "] 7 (#$ . 311527) nil])#@62 Insert a package specification or body. (fn &optional KIND) (defalias 'vhdl-template-package #[256 "\304 `\305\211\211\306\307!\210\203�\310=\202�\311\305\312\"\313=\262\203H�\306\314!\210\212\315\316 p\317\320#\216\321 !\210\322\323\305\315#)\266\202*\203H�\324\325!\211\262c\210\204Z�\326\327\305\315`%\211\262\205\235�\306\330!\210\n\331>\203g�\332c\210 \\j\210`\262\332c\210\n\333>\203{�\332c\210j\210\306\334!\210\335\336!\204\222�\306\307\205\217�\314P!\210\206\227�\337\340\261\210\211b\207" [case-fold-search vhdl-mode-ext-syntax-table vhdl-insert-empty-lines vhdl-basic-offset current-indentation nil vhdl-insert-keyword "PACKAGE " body vhdl-decision-query "(d)eclaration or (b)ody?" 98 "BODY " t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table vhdl-re-search-backward "\\<package \\(\\w+\\) is\\>" match-string 1 vhdl-template-field "name" " IS\n" (unit all) "\n" (unit all) "END " vhdl-standard-p 87 "" ";"] 12 (#$ . 311839) nil])#@33 Insert a package specification. (defalias 'vhdl-template-package-decl #[0 "\300\301!\207" [vhdl-template-package decl] 2 (#$ . 312861) nil])#@24 Insert a package body. (defalias 'vhdl-template-package-body #[0 "\300\301!\207" [vhdl-template-package body] 2 (#$ . 313007) nil])#@69 Insert a port declaration, or port map in instantiation statements. (defalias 'vhdl-template-port #[0 "`\302\303 p\304\305#\216\306 !\210\212\307\310\311\302#)\203)�\312\313!\226\314\232\203)�\315\311!\202L�\212\316 \2062�\317\320!)\204?�\321 @@\322=\203I�\323\324!\210\325!\202L�\315\311!)\266\202)\207" [case-fold-search vhdl-mode-ext-syntax-table t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table re-search-backward "^\\(entity\\|end\\)\\>" nil match-string 1 "ENTITY" vhdl-template-port-list beginning-of-line looking-at "^\\s-*\\w+\\s-*:\\s-*\\w+" vhdl-get-syntactic-context statement-cont vhdl-insert-keyword "PORT " vhdl-template-map] 7 (#$ . 313144) nil])#@22 Insert a procedural. (defalias 'vhdl-template-procedural #[0 "\302 `\303\304\305\306!\210 \307>\2030�b\210\310c\210b\210\311\312\304\303#\262\211\204)�\313\314!\210\315\316!\210\316u\210\317\320!\204:�\305\321!\210\322c\210\323\324#\210\325 )\207" [case-fold-search vhdl-optional-labels current-indentation t nil vhdl-insert-keyword "PROCEDURAL " (process all) ": " vhdl-template-field "[label]" delete-char 2 forward-word-strictly 1 vhdl-standard-p 87 "IS" "\n" vhdl-template-begin-end "PROCEDURAL" vhdl-comment-block] 8 (#$ . 313871) nil])#@62 Insert a procedure declaration or body. (fn &optional KIND) (defalias 'vhdl-template-procedure #[256 "\301 `\302\303\304!\210\305\306\302\307`%\211\262\205^�\310 \210\203\"�\311=\202(�\312\302\313\"\314=\203O�\303\315!\210\2039�\316`\317#\210\302\210\320c\210\321\322\323!?\205H�\324#\210\325 \207\326c\210\203\\�\316`\317#\210\302\207" [vhdl-auto-align current-indentation nil vhdl-insert-keyword "PROCEDURE " vhdl-template-field "name" t vhdl-template-argument-list body vhdl-decision-query "(d)eclaration or (b)ody?" 98 " IS" vhdl-align-region-groups 1 "\n" vhdl-template-begin-end vhdl-standard-p 87 "PROCEDURE" vhdl-comment-block ";"] 10 (#$ . 314426) nil])#@33 Insert a procedure declaration. (defalias 'vhdl-template-procedure-decl #[0 "\300\301!\207" [vhdl-template-procedure decl] 2 (#$ . 315107) nil])#@26 Insert a procedure body. (defalias 'vhdl-template-procedure-body #[0 "\300\301!\207" [vhdl-template-procedure body] 2 (#$ . 315257) nil])#@40 Insert a process. (fn &optional KIND) (defalias 'vhdl-template-process #[256 "\306 `\307\211\211\211\211\211 \203� \310=\202�\311\312\313\314#\315=\262\316\317!\210 \320>\203J�b\210\321c\210b\210\322\323\307\314#\262\204C�\324\325!\210\326\327!\210\327u\210\330c\210\204z�\331\332!\203e�\n\203e�\333c\210\334\211\262\204\313�\322\335\336\314#\211\262\204\313�\337\262\324\340!\210\202\313� \337\232\204\207� c\210 \206\216�\322\341!\206\216�\342\262\343=\203\250�\311\337\344\314#\345=\203\245�\346\202\246�\347\262\346=\203\310�\350c\210\f\337\232\204\277�\fc\210\f\206\306�\322\351!\206\306�\352\262\336c\210\331\353!\204\325�\316\354!\210\355c\210\356\357 #\210\203\354�\360 #\262 \205\240\361 \262\314@\362 p\363\364#\216\365A!\210\366\367\307\314#\203\233\366\370\307\314#\203\233\371\210o\203%\355c\210\372y\210\202(\355c\210\nj\210\373c\210\322\374\307\314#\204=\375 \210\202\233\355c\210\nj\210\376c\210\203P\377\202S\201B�\355\261\210\nj\210\201C�c\210\204kc\210\202\207\350\261\210\203y\350\261\210\322\201D�\307\314#\204\207\324\340!\210\355c\210\nj\210\201E�c\210\322\201D�\307\314#\210*\266\211b\207" [vhdl-reset-kind vhdl-optional-labels vhdl-sensitivity-list-all vhdl-clock-name vhdl-reset-name vhdl-prompt-for-comments current-indentation nil seq vhdl-decision-query "process" "(c)ombinational or (s)equential?" t 115 vhdl-insert-keyword "PROCESS " (process all) ": " vhdl-template-field "[label]" delete-char 2 forward-word-strictly 1 "(" vhdl-standard-p 8 "all)" "all" "[sensitivity list]" ")" "" -2 "clock name" "<clock>" query "(a)synchronous or (s)ynchronous reset?" 97 async sync ", " "reset name" "<reset>" 87 " IS" "\n" vhdl-template-begin-end "PROCESS" vhdl-template-seq-process point-marker syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table vhdl-re-search-backward "\\<begin\\>" "\\<process\\>" 0 -1 "-- purpose: " "[description]" vhdl-line-kill-entire "-- type : " "sequential" case-fold-search vhdl-mode-ext-syntax-table "combinational" "-- inputs : " "[signal names]" "-- outputs: "] 16 (#$ . 315400) nil])#@33 Insert a combinational process. (defalias 'vhdl-template-process-comb #[0 "\300\301!\207" [vhdl-template-process comb] 2 (#$ . 317562) nil])#@30 Insert a sequential process. (defalias 'vhdl-template-process-seq #[0 "\300\301!\207" [vhdl-template-process seq] 2 (#$ . 317708) nil])#@32 Insert a quantity declaration. (defalias 'vhdl-template-quantity #[0 "\300 \203'�`\301\302!\210\303\304\305\306`%\205&�\307c\210\303\310\311\306#\210\303\312!\210\313c\210\314 \207\315\316\317\306#\211\320\267\202;�\321 \207\322 \207\323 \207\324``\"\207" [vhdl-in-argument-list-p vhdl-insert-keyword "QUANTITY " vhdl-template-field "names" nil t " : " "[IN | OUT]" " " "type" ";" vhdl-comment-insert-inline vhdl-decision-query "quantity" "(f)ree, (b)ranch, or (s)ource quantity?" #s(hash-table size 3 test eq rehash-size 1.5 rehash-threshold 0.8125 purecopy t data (102 50 98 53 115 56)) vhdl-template-quantity-free vhdl-template-quantity-branch vhdl-template-quantity-source vhdl-template-undo] 7 (#$ . 317849) nil])#@37 Insert a free quantity declaration. (defalias 'vhdl-template-quantity-free #[0 "\300\301!\210\302\303!\210\304c\210\302\305!\210`\306c\210\302\307\310\311#\204�\211`|\210\312c\210\313 \207" [vhdl-insert-keyword "QUANTITY " vhdl-template-field "names" " : " "type" " := " "[initialization]" nil t ";" vhdl-comment-insert-inline] 5 (#$ . 318574) nil])#@39 Insert a branch quantity declaration. (defalias 'vhdl-template-quantity-branch #[0 "\300\301\302!\210\303\304\305\306#\203�\301\307!\210\303\310\305\306#\203�\301\311!\210\303\312!\210`\262\301\313!\210\303\314\300\306#\2044�\211`|\210\315c\210\316 \207" [nil vhdl-insert-keyword "QUANTITY " vhdl-template-field "[across names]" " " t "ACROSS " "[through names]" "THROUGH " "plus terminal name" " TO " "[minus terminal name]" ";" vhdl-comment-insert-inline] 5 (#$ . 318930) nil])#@39 Insert a source quantity declaration. (defalias 'vhdl-template-quantity-source #[0 "\300\301!\210\302\303!\210\304c\210\302\305\306\"\210\307\310\311\"\312=\203$�\300\313!\210\302\314!\210\2021�\300\315!\210\302\316\317\"\210\302\320!\210\321c\210\322 \207" [vhdl-insert-keyword "QUANTITY " vhdl-template-field "names" " : " "type" " " vhdl-decision-query nil "(s)pectrum or (n)oise?" 110 "NOISE " "power expression" "SPECTRUM " "magnitude expression" ", " "phase expression" ";" vhdl-comment-insert-inline] 3 (#$ . 319418) nil])#@71 Insert a record type declaration. (fn KIND &optional NAME SECONDARY) (defalias 'vhdl-template-record #[769 "\302 `\303\304\305!\210\\j\210\306\307\310?`%\204�\205t�\211\204)�\306\311\310\303#\203M�\312c\210\306\313=\2038�\314\2029�\315\316\"\210\317 \210\320c\210\\j\210\310\262\202�\321 `|\210j\210\304\322!\210\323\324!\204h�\203h�\325\261\210\316c\210 \205t�\326`\327#\207" [vhdl-basic-offset vhdl-auto-align current-indentation t vhdl-insert-keyword "RECORD\n" vhdl-template-field "element names" nil "[element names]" " : " type "type" "nature" ";" vhdl-comment-insert-inline "\n" line-beginning-position "END RECORD" vhdl-standard-p 87 " " vhdl-align-region-groups 1] 12 (#$ . 319953) nil])#@28 Insert a report statement. (defalias 'vhdl-template-report #[0 "`\300\301!\210\302\303\304\305`\305&\306\232\203�\307\310!\207`\262\300\311!\210\302\312\304\305#\204*�\211`|\210\313c\207" [vhdl-insert-keyword "REPORT " vhdl-template-field "string expression" nil t "\"\"" delete-char -2 " SEVERITY " "[NOTE | WARNING | ERROR | FAILURE]" ";"] 8 (#$ . 320674) nil])#@28 Insert a return statement. (defalias 'vhdl-template-return #[0 "`\300\301!\210\302\303\304\305`%\204�\306\307!\210\310c\207" [vhdl-insert-keyword "RETURN " vhdl-template-field "[expression]" nil t delete-char -1 ";"] 7 (#$ . 321047) nil])#@38 Insert a selected signal assignment. (defalias 'vhdl-template-selected-signal-asst #[0 "\302 `\303`\304\305!\210\211b\266\304\306!\210\307\310\311\303`\312\\%\205\223�\313\314!\210\315\314!\210\316c\210\\j\210\307\317\320\"\210\316c\210\\j\210\307\321!\210\304\322!\210\307\323\324\"\210\316c\210\\j\210\211\203|�\307\325\311\303#\203|�\304\322!\210\307\326\324\303#\211\262\203u�\316c\210\\j\210\202O�\304\327!\210\202O�\211\203\207�\330 \210\315\331!\210\332c\210 \205\223�\333`\314#\207" [vhdl-basic-offset vhdl-auto-align current-indentation t vhdl-insert-keyword " SELECT " "WITH " vhdl-template-field "selector expression" nil 7 forward-word-strictly 1 delete-char "\n" "target signal" " <= " "waveform" " WHEN " "choices" "," "[waveform]" "[choices]" "OTHERS" fixup-whitespace -2 ";" vhdl-align-region-groups] 10 (#$ . 321293) nil])#@30 Insert a signal declaration. (defalias 'vhdl-template-signal #[0 "`\300 \301\302!\210\303\304\305\306`%\205C�\307c\210\211\203�\303\310\311\306#\210\303\312!\210\211\203,�\313c\210\314 \207`\315c\210\303\316\305\306#\204<�\211`|\210\313c\210\314 \262\207" [vhdl-in-argument-list-p vhdl-insert-keyword "SIGNAL " vhdl-template-field "names" nil t " : " "[IN | OUT | INOUT]" " " "type" ";" vhdl-comment-insert-inline " := " "[initialization]"] 8 (#$ . 322150) nil])#@33 Insert a subnature declaration. (defalias 'vhdl-template-subnature #[0 "`\300\301\302!\210\303\304\300\305`%\205^�\301\306!\210\303\307\310\"\210\303\311\300\305#\203'�\312c\210\202+�\313\314!\210`\262\301\315!\210\303\316\300\305\300\211\305&\317\232\203G�\211`|\210\202Y�\301\320!\210\303\321\300\211\211\211\305&\210\301\322!\210\323c\210\324 \207" [nil vhdl-insert-keyword "SUBNATURE " vhdl-template-field "name" t " IS " "nature" " (" "[index range]" ")" delete-char -2 " TOLERANCE " "[string expression]" "\"\"" " ACROSS " "string expression" " THROUGH" ";" vhdl-comment-insert-inline] 9 (#$ . 322621) nil])#@27 Insert a subprogram body. (defalias 'vhdl-template-subprogram-body #[0 "\300\301\302\303#\304=\203 �\305 \207\306 \207" [vhdl-decision-query nil "(p)rocedure or (f)unction?" t 102 vhdl-template-function-body vhdl-template-procedure-body] 4 (#$ . 323244) nil])#@34 Insert a subprogram declaration. (defalias 'vhdl-template-subprogram-decl #[0 "\300\301\302\303#\304=\203 �\305 \207\306 \207" [vhdl-decision-query nil "(p)rocedure or (f)unction?" t 102 vhdl-template-function-decl vhdl-template-procedure-decl] 4 (#$ . 323509) nil])#@31 Insert a subtype declaration. (defalias 'vhdl-template-subtype #[0 "`\300\301!\210\302\303\304\305`%\205)�\300\306!\210\302\307\310\"\210\302\311\304\305#\204$�\312\313!\210\314c\210\315 \207" [vhdl-insert-keyword "SUBTYPE " vhdl-template-field "name" nil t " IS " "type" " " "[RANGE value range | ( index range )]" delete-char -1 ";" vhdl-comment-insert-inline] 7 (#$ . 323781) nil])#@32 Insert a terminal declaration. (defalias 'vhdl-template-terminal #[0 "`\300\301!\210\302\303\304\305`%\205�\306c\210\302\307!\210\310c\210\311 \207" [vhdl-insert-keyword "TERMINAL " vhdl-template-field "names" nil t " : " "nature" ";" vhdl-comment-insert-inline] 7 (#$ . 324172) nil])#@28 Insert a type declaration. (defalias 'vhdl-template-type #[0 "`\300\211\211\301\302!\210\303\304\300\305`%\211\262\205\235�\301\306!\210\303\307\300\305#\206#�\310\226\211\311\267\202\201�\312\313!\210\314c\210\202\204�`\315\316!\210`|\210\317\320\305\"\210\202\204�\321 \262`\315\316!\210`|\210\322\320\305#\210\202\204�\323c\210\303\324\314\"\210\202\204�\301\325!\210\303\324\314\"\210\202\204�\326\316!\210\327c\210\321 \262\330c\210\202\204�\314c\210\203\222�\321 \262b\210\300\210\331 \210\205\233�b\262\207" [nil vhdl-insert-keyword "TYPE " vhdl-template-field "name" t " IS " "[scalar type | ARRAY | RECORD | ACCESS | FILE | ENUM]" #1="" #s(hash-table size 6 test equal rehash-size 1.5 rehash-threshold 0.8125 purecopy t data (#1# 42 "ARRAY" 52 "RECORD" 68 "ACCESS" 89 "FILE" 100 "ENUM" 112)) delete-char -4 ";" forward-word-strictly -1 vhdl-template-array type point-marker vhdl-template-record " " "type" " OF " kill-word "(" ");" vhdl-comment-insert-inline] 10 (#$ . 324464) nil])#@22 Insert a use clause. (defalias 'vhdl-template-use #[0 "`\302\303 p\304\305#\216\306 !\210\307\310!\210\212\311 \210\312\313!)\205<�\307\314!\210\315u\210\316\317\320\302`\321\\%\205<�\322u\210\316\323!\210\324u)\266\202)\207" [case-fold-search vhdl-mode-ext-syntax-table t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table vhdl-insert-keyword "USE " beginning-of-line looking-at "^\\s-*use\\>" "..ALL;" -6 vhdl-template-field "library name" nil 6 1 "package name" 5] 10 (#$ . 325474) nil])#@32 Insert a variable declaration. (defalias 'vhdl-template-variable #[0 "`\302 \303\304 p\305\306#\216\307 !\210\212\310 \210\311\312!)\204)�\212\313\314!\210\311\315!)\2030�\316\317!\210\202A�\320\321!\203=�\322\323!\210\202A�\316\324!\210*\266\325\326\327\303`%\205\200�\330c\210\211\203[�\325\331\332\303#\210\325\333!\210\211\203i�\334c\210\335 \207`\336c\210\325\337\327\303#\204y�\211`|\210\334c\210\335 \262\207" [case-fold-search vhdl-mode-ext-syntax-table vhdl-in-argument-list-p t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table vhdl-beginning-of-block looking-at "\\s-*\\(\\w+\\s-*:\\s-*\\)?\\<\\(\\<function\\|procedure\\|process\\|procedural\\)\\>" backward-word-strictly 1 "\\<shared\\>" vhdl-insert-keyword "VARIABLE " vhdl-standard-p 87 error "ERROR: Not within sequential block" "SHARED VARIABLE " vhdl-template-field "names" nil " : " "[IN | OUT | INOUT]" " " "type" ";" vhdl-comment-insert-inline " := " "[initialization]"] 8 (#$ . 326026) nil])#@26 Insert a wait statement. (defalias 'vhdl-template-wait #[0 "\300\301!\210\302\303\304\305#\204�\306\307!\210\310c\207" [vhdl-insert-keyword "WAIT " vhdl-template-field "[ON sensitivity list] [UNTIL condition] [FOR time expression]" nil t delete-char -1 ";"] 4 (#$ . 327054) nil])#@46 Indent correctly if within a case statement. (defalias 'vhdl-template-when #[0 "`\303\304\305 p\306\307#\216\310 !\210i\311 U\2038�\312\313\303\304#\2038�\314\315!\2038�\311 \262b\210\316 \210\n\\j\210\202;�b\210*\266\317\320!\207" [case-fold-search vhdl-mode-ext-syntax-table vhdl-basic-offset nil t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table current-indentation vhdl-re-search-forward "\\<end\\>" looking-at "\\s-*\\<case\\>" delete-horizontal-space vhdl-insert-keyword "WHEN "] 8 (#$ . 327340) nil])#@22 Insert a while loop. (defalias 'vhdl-template-while-loop #[0 "\303 `\304\305=\204�\306\307!\210\202.�\306\310!\210b\210\311\312\304\313#\262\211\204'�\314\315!\210\316\317!\210\317u\210 \2035�\320c\210\311\321\304\313`%\205f� \203F�\322c\210\306\323!\210j\210\306\324!\210\211\203\\�\325\326Q\202]�\326c\210\327y\210\n\\j\207" [vhdl-optional-labels vhdl-conditions-in-parenthesis vhdl-basic-offset current-indentation nil all vhdl-insert-keyword "WHILE " ": WHILE " vhdl-template-field "[label]" t delete-char 2 forward-word-strictly 1 "(" "condition" ")" " LOOP\n\n" "END LOOP" " " ";" -1] 9 (#$ . 327915) nil])#@60 Insert a with statement (i.e. selected signal assignment). (defalias 'vhdl-template-with #[0 "\302\303 p\304\305#\216\306 !\210\212\307\310!)\203$�\311\312!\313\232\203$�\314 \202'�\315\316!)\266\202)\207" [case-fold-search vhdl-mode-ext-syntax-table t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table vhdl-re-search-backward "\\(\\<limit\\>\\|;\\)" match-string 1 ";" vhdl-template-selected-signal-asst vhdl-insert-keyword "WITH "] 6 (#$ . 328541) nil])#@56 Insert a wait statement for rising/falling clock edge. (defalias 'vhdl-template-clocked-wait #[0 "`\304\305\306!\210\307\232\204�c\210\206�\310\311\304\312`%\211\262\205E�\313c\210\305\314!\210\211c\210\315 \2033�\n\2024� \316\261\210\317 \203A�\320\202B�\321\322P!\207" [vhdl-clock-name vhdl-clock-rising-edge vhdl-one-string vhdl-zero-string nil vhdl-insert-keyword "WAIT UNTIL " "" vhdl-template-field "clock name" t "'event" " AND " " = " ";" vhdl-comment-insert-inline "rising" "falling" " clock edge"] 8 (#$ . 329057) nil])#@86 Insert a template for the body of a sequential process. (fn CLOCK RESET RESET-KIND) (defalias 'vhdl-template-seq-process #[771 "\306 \307\310\311!\210\203�\312c\210\313=\203X�\314 \203�\n\202� \261\210\203)�\315c\210\310\316!\210\317\320 \2037�\321\2028�\322\315Q!\210\323c\210\f\\j\210`\262\323c\210j\210\310\324!\210\203X�\312c\210 \325=\203r�&\203g�\326\202h�\327\330\315\261\210\202\212�\331\261\210\310\332!\210\314&\203\206�\n\202\207� \261\210\203\221�\315c\210\310\316!\210\317&\203\237�\326\202\240�\327\333P!\210\323c\210\f\\j\210\334=\203,\310\311!\210\203\275�\312c\210'\335\232\204\315�'c\210'\206\324�\336\337!\206\324�\340\262\314 \203\337�\n\202\340� \261\210\203\352�\315c\210\310\316!\210\317\341 \203\370�\321\202\371�\322\315Q!\210\323c\210\342\f_\\j\210`\262\323c\210\f\\j\210\310\343!\210\323c\210\342\f_\\j\210\323c\210\f\\j\210\310\344!\210\345=\2035`\262\323c\210j\210\310\344!\210\211b\210\207" [vhdl-conditions-in-parenthesis vhdl-reset-active-high vhdl-one-string vhdl-zero-string vhdl-basic-offset vhdl-clock-edge-condition current-indentation nil vhdl-insert-keyword "IF " "(" async " = " ")" " THEN" vhdl-comment-insert-inline "asynchronous reset (active " "high" "low" "\n" "ELSIF " function "rising" "falling" "_edge(" "'event" " AND " " clock edge" sync "" vhdl-template-field "reset name" "<reset>" "synchronous reset (active " 2 "ELSE" "END IF;" none vhdl-clock-rising-edge vhdl-reset-name] 9 (#$ . 329600)])#@122 Insert specification of a standard package. Include a library specification, if not already there. (fn LIBRARY PACKAGE) (defalias 'vhdl-template-standard-package #[514 "\302 \303\232\204M�\212\304\305 p\306\307#\216\310 !\210o?\205,�\311\312\313Q\314\304#\205,�\315\316!)\266\202*\204M�\227\317\232\204M�\320\321!\210\322\261\210\203M�\323c\210\211j\210\205^�\320\324!\210\325\261\210\320\326!\207" [case-fold-search vhdl-mode-ext-syntax-table current-indentation "std" t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table re-search-backward "^\\s-*\\(\\(library\\)\\s-+\\(\\w+\\s-*,\\s-*\\)*" "\\|end\\)\\>" nil match-string 2 "work" vhdl-insert-keyword "LIBRARY " ";" "\n" "USE " "." ".ALL;"] 9 (#$ . 331095)])#@48 Insert specification of `numeric_bit' package. (defalias 'vhdl-template-package-numeric-bit #[0 "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "numeric_bit"] 3 (#$ . 331879) nil])#@48 Insert specification of `numeric_std' package. (defalias 'vhdl-template-package-numeric-std #[0 "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "numeric_std"] 3 (#$ . 332077) nil])#@51 Insert specification of `std_logic_1164' package. (defalias 'vhdl-template-package-std-logic-1164 #[0 "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "std_logic_1164"] 3 (#$ . 332275) nil])#@52 Insert specification of `std_logic_arith' package. (defalias 'vhdl-template-package-std-logic-arith #[0 "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "std_logic_arith"] 3 (#$ . 332482) nil])#@51 Insert specification of `std_logic_misc' package. (defalias 'vhdl-template-package-std-logic-misc #[0 "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "std_logic_misc"] 3 (#$ . 332692) nil])#@53 Insert specification of `std_logic_signed' package. (defalias 'vhdl-template-package-std-logic-signed #[0 "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "std_logic_signed"] 3 (#$ . 332899) nil])#@53 Insert specification of `std_logic_textio' package. (defalias 'vhdl-template-package-std-logic-textio #[0 "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "std_logic_textio"] 3 (#$ . 333112) nil])#@55 Insert specification of `std_logic_unsigned' package. (defalias 'vhdl-template-package-std-logic-unsigned #[0 "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "std_logic_unsigned"] 3 (#$ . 333325) nil])#@43 Insert specification of `textio' package. (defalias 'vhdl-template-package-textio #[0 "\300\301\302\"\207" [vhdl-template-standard-package "std" "textio"] 3 (#$ . 333544) nil])#@58 Insert specification of `fundamental_constants' package. (defalias 'vhdl-template-package-fundamental-constants #[0 "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "fundamental_constants"] 3 (#$ . 333726) nil])#@55 Insert specification of `material_constants' package. (defalias 'vhdl-template-package-material-constants #[0 "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "material_constants"] 3 (#$ . 333954) nil])#@51 Insert specification of `energy_systems' package. (defalias 'vhdl-template-package-energy-systems #[0 "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "energy_systems"] 3 (#$ . 334173) nil])#@55 Insert specification of `electrical_systems' package. (defalias 'vhdl-template-package-electrical-systems #[0 "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "electrical_systems"] 3 (#$ . 334380) nil])#@55 Insert specification of `mechanical_systems' package. (defalias 'vhdl-template-package-mechanical-systems #[0 "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "mechanical_systems"] 3 (#$ . 334599) nil])#@52 Insert specification of `radiant_systems' package. (defalias 'vhdl-template-package-radiant-systems #[0 "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "radiant_systems"] 3 (#$ . 334818) nil])#@52 Insert specification of `thermal_systems' package. (defalias 'vhdl-template-package-thermal-systems #[0 "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "thermal_systems"] 3 (#$ . 335028) nil])#@52 Insert specification of `fluidic_systems' package. (defalias 'vhdl-template-package-fluidic-systems #[0 "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "fluidic_systems"] 3 (#$ . 335238) nil])#@49 Insert specification of `math_complex' package. (defalias 'vhdl-template-package-math-complex #[0 "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "math_complex"] 3 (#$ . 335448) nil])#@46 Insert specification of `math_real' package. (defalias 'vhdl-template-package-math-real #[0 "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "math_real"] 3 (#$ . 335649) nil])#@35 Insert directive. (fn DIRECTIVE) (defalias 'vhdl-template-directive #[257 "\300 iU\204 �\301 \210\302c\210\303\261\207" [current-indentation delete-horizontal-space " " "-- pragma "] 3 (#$ . 335841)])#@34 Insert directive `translate_on'. (defalias 'vhdl-template-directive-translate-on #[0 "\300\301!\207" [vhdl-template-directive "translate_on"] 2 (#$ . 336051) nil])#@35 Insert directive `translate_off'. (defalias 'vhdl-template-directive-translate-off #[0 "\300\301!\207" [vhdl-template-directive "translate_off"] 2 (#$ . 336220) nil])#@34 Insert directive `synthesis_on'. (defalias 'vhdl-template-directive-synthesis-on #[0 "\300\301!\207" [vhdl-template-directive "synthesis_on"] 2 (#$ . 336392) nil])#@35 Insert directive `synthesis_off'. (defalias 'vhdl-template-directive-synthesis-off #[0 "\300\301!\207" [vhdl-template-directive "synthesis_off"] 2 (#$ . 336561) nil])#@55 Insert a VHDL file header. (fn &optional FILE-TITLE) (defalias 'vhdl-template-header #[256 "\301\232?\205�\302\212eb\210\303!\210\304 )\262\305\306 #\262\207" [vhdl-file-header "" nil vhdl-insert-string-or-file point-marker vhdl-template-replace-header-keywords point-min-marker] 6 (#$ . 336733) nil])#@28 Insert a VHDL file footer. (defalias 'vhdl-template-footer #[0 "\301\232?\205%�\302\212db\210\303 \262\304!\210h\305U\204�\306c\210)\307\310 \"\262\207" [vhdl-file-footer "" nil point-marker vhdl-insert-string-or-file 10 "\n" vhdl-template-replace-header-keywords point-max-marker] 4 (#$ . 337048) nil])#@84 Replace keywords in header and footer. (fn BEG END &optional FILE-TITLE IS-MODEL) (defalias 'vhdl-template-replace-header-keywords #[1026 "\306 \"@\206 �\307\310\306 \"8\206�\307\311\312\313 p\314\315#\216\316 !\210\212b\210\317\320 \312#\203:�\321\312\211#\210\202(�b\210\317\322 \312#\203Q�\321\323 \312\211#\210\202>�b\210\317\324 \312#\203g�\321\f\312\211#\210\202U�b\210\317\325 \312#\203\213�\321\307\312\211#\210\326 c\210 \203k�\327 \330\261\210\202k�b\210\317\331 \312#\203\242�\321\326 \312\211#\210\202\217�b\210\317\332 \312#\203\271�\321\333 \312\211#\210\202\246�b\210\317\334 \312#\203\317�\321\312\211#\210\202\275�b\210\317\335 \312#\203\346�\321@\312\211#\210\202\323�b\210\317\336 \312#\203\375�\321A\312\211#\210\202\352�b\210\317\337 \312#\203=\321\340\341\342!\203\343\202'\341\344!\203 \345\202'\341\346!\205'\347\341\350!\205.\351\341\352!\2055\353R\312\211#\210\202b\210\317\354 \312#\203S\321\355\311\312#\210\202Ab\210\317\356 \312#\203l\321\307\312\211#\210\357 \210\202Wb\210\360\361!\317\362\n\312#\203\205\321\312\211#\210\202s\210b\210\203\246\317\363 \312#\203\242\321\312\211#\210\202\217b\210\311\364\365\n\312#\203\312\366 \314\367\"\216\370\371\372!\373P!)\266\202\321\312\211#\210\202\247\210b\210\204\345\317\374 \312#\203\345\321\307\312\211#\210`\262)\203\355b\210?\205'\203\374\307\232\203�\375\376!\210\203\n\307\232\203\375\377!\210A\307\232\203\375\201B�!\210@\307\232\205'\375\201C�!)\266\202)\207" [vhdl-project-alist vhdl-project case-fold-search vhdl-mode-ext-syntax-table vhdl-copyright-string user-mail-address vhdl-aget "" 9 nil t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table search-forward "<projectdesc>" replace-match "<filename>" buffer-name "<copyright>" "<author>" user-full-name " <" ">" "<authorfull>" "<login>" user-login-name "<project>" "<company>" "<platform>" "<standard>" "VHDL" vhdl-standard-p 87 "'87" 93 "'93/02" 8 "'08" ams ", VHDL-AMS" math ", Math Packages" "<RCS>" "$" "<date>" vhdl-template-insert-date format-time-string "%Y" "<year>" "<title string>" re-search-forward "<\\(\\(\\w\\|\\s_\\)*\\) string>" match-data #[0 "\301\300\302\"\207" [V0 set-match-data t] 3] read-string match-string 1 ": " "<cursor>" message "You can specify a project title in user option `vhdl-project-alist'" "You can specify a project description in user option `vhdl-project-alist'" vhdl-company-name vhdl-platform-spec "You can specify a platform in user option `vhdl-platform-spec'" "You can specify a company name in user option `vhdl-company-name'"] 15 (#$ . 337363)])#@18 Indent comments. (defalias 'vhdl-comment-indent #[0 "`\301y\210\302\303\304#\203�i\305Z\202�\211b\210\306\307x\210iT]b\210\207" [comment-column -1 re-search-forward "--" t 2 " " nil] 5 (#$ . 340066)])#@153 Start a comment at the end of the line. If on line with code, indent at least `comment-column'. If starting after end-comment-column, start a new line. (defalias 'vhdl-comment-insert #[0 "iV\203 �\303 \210\304\305!\204� \204J�\306\204J�\306h\307U\203&�\310\311!\210\202�i\262\312 \210n\2039�\211j\210\313c\210\202B�\314c\210\nj\210\313c\210 ?\205I�\315c\207\306\211h\307U\203Y�\310\316!\210\202L�\317 \211\262\320U\203v�\313c\210\316u\210\321y\210\322\323!\210\324\262\202Y�\211\204}�\313c\210\325! B\211\207" [end-comment-column unread-command-events comment-column newline-and-indent looking-at "\\s-*$" nil 45 delete-char -1 delete-horizontal-space "--" " " " " -2 read-char 13 1 message "Enter CR if commenting out a line of code." t vhdl-character-to-event] 4 (#$ . 340279) nil])#@98 Add 2 comment lines at the current indent, making a display comment. (fn &optional LINE-EXISTS) (defalias 'vhdl-comment-display #[256 "\300 \204 �\301 \210\302c\210\211j\210\302c\210\211j\210\301 \210\303\210\304c\207" [current-indentation vhdl-comment-display-line "\n" 0 "-- "] 3 (#$ . 341079) nil])#@30 Displays one line of dashes. (defalias 'vhdl-comment-display-line #[0 "h\302U\203 �\303\304!\210\202��\305c\210iZ\306 \"\207" [end-comment-column vhdl-comment-display-line-char 45 delete-char -2 "--" insert-char] 5 (#$ . 341389) nil])#@46 Append empty inline comment to current line. (defalias 'vhdl-comment-append-inline #[0 "\301\210\302 \210\303c\210j\210\304c\207" [comment-column nil delete-horizontal-space " " "-- "] 1 (#$ . 341632) nil])#@61 Insert inline comment. (fn &optional STRING ALWAYS-INSERT) (defalias 'vhdl-comment-insert-inline #[512 "\203\f�\204�\211\204�?\205F� \205F�`\303c\210\nj\210\304c\210\203)�c\210\2027�\305\306\307\310#\2047�\211`|\202D�h\311U\205D�\312\313!\210\2027�\262\207" [vhdl-self-insert-comments vhdl-prompt-for-comments comment-column " " "-- " vhdl-template-field "[comment]" nil t 32 delete-char -1] 7 (#$ . 341847)])#@32 Insert comment for code block. (defalias 'vhdl-comment-block #[0 "\205X�\303 \304\305 p\306\307#\216\310\n!\210\311\312\313\304#\203Q�\311\314\313\304#\203Q�\313\315 \210i\262\316\210o\203<�\317c\210\320y\210\202?�\317c\210\211j\210\321c\210\322\323\313\304#\204P�\324 \210\210*\266\211b\262\207" [vhdl-prompt-for-comments case-fold-search vhdl-mode-ext-syntax-table point-marker t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table re-search-backward "^\\s-*begin\\>" nil "\\<\\(architecture\\|block\\|function\\|procedure\\|process\\|procedural\\)\\>" back-to-indentation 0 "\n" -1 "-- purpose: " vhdl-template-field "[description]" vhdl-line-kill-entire] 8 (#$ . 342272)])#@91 Comment out region if not commented out, uncomment otherwise. (fn BEG END &optional ARG) (defalias 'vhdl-comment-uncomment-region #[770 "\212Sb\210\301\210\302 \262b\210\303 \210`\262\304\305P!\203%�\306\307#\202)�\306\")\207" [comment-start nil point-marker beginning-of-line looking-at "\\s-*" comment-region (4)] 7 (#$ . 343012) "r"])#@81 Comment out line if not commented out, uncomment otherwise. (fn &optional ARG) (defalias 'vhdl-comment-uncomment-line #[256 "\212\300 \210`\206\n�\301y\210\302`\")\207" [beginning-of-line 1 vhdl-comment-uncomment-region] 5 (#$ . 343366) "p"])#@40 Kill comments in region. (fn BEG END) (defalias 'vhdl-comment-kill-region #[514 "\212\211b\210\300 \262b\210\301 \210`W\205*�\302\303!\203#�\304\224\304\225|\210\202�\301\305!\210\202�)\207" [point-marker beginning-of-line looking-at "^\\(\\s-*--.*\n\\)" 1 2] 4 (#$ . 343617) "r"])#@47 Kill inline comments in region. (fn BEG END) (defalias 'vhdl-comment-kill-inline-region #[514 "\212\211b\210\300 \262b\210\301 \210`W\205'�\302\303!\203 �\304\224\304\225|\210\301\305!\210\202�)\207" [point-marker beginning-of-line looking-at "^.*[^ \n \f-]+\\(\\s-*--.*\\)$" 1 2] 4 (#$ . 343910) "r"])#@141 Insert a begin ... end pair with optional name after the end. Point is left between them. (fn CONSTRUCT NAME MARGIN &optional EMPTY-LINES) (defalias 'vhdl-template-begin-end #[1027 "\303\204 �\304=\203�\305c\210j\210\306\307!\210\204�\2038� \2038�\310c\210\203/�\311c\210\306!\210\2038�\311\261\210\305c\210\204E�\304=\203H�\305c\210\n\\j\210`\262\305c\210\204]�\304=\203`�\305c\210j\210\306\312!\210\203r�\311c\210\306!\210\203|�\311P\202}�\313\314\261\210\211b\207" [vhdl-insert-empty-lines vhdl-self-insert-comments vhdl-basic-offset nil all "\n" vhdl-insert-keyword "BEGIN" " --" " " "END" "" ";"] 7 (#$ . 344225)])#@83 Read from user a procedure or function argument list. (fn &optional IS-FUNCTION) (defalias 'vhdl-template-argument-list #[256 "\302c\210i`\303\211\211\204�\304 \\\262\305c\210j\210\306\307?\205!�\310\311Q\312\313#\262\306\314\303\313#\203{�\313\262\315c\210\204R�\203L�\226\316\232\203L�\317\320!\210\202R�\306\321\312\313#\210\306\322!\210`\262\323c\210\324 \210`\262\305c\210j\210\306\307?\205q�\310\311Q\312\313#\262\202(�`|\210\211\203\206�\211b\210\203\221�\325\326!\210\327c\207\325\330!\207" [vhdl-argument-list-indent vhdl-basic-offset " (" nil current-indentation "\n" vhdl-template-field "[CONSTANT | SIGNAL" " | VARIABLE" "]" " " t "[names]" " : " "CONSTANT" vhdl-insert-keyword "IN " "[IN | OUT | INOUT]" "type" ";" vhdl-comment-insert-inline delete-char 1 ")" -2] 10 (#$ . 344876)])#@80 Read from user a generic spec argument list. (fn OPTIONAL &optional NO-VALUE) (defalias 'vhdl-template-generic-list #[513 "\303`\304\305!\210i\262\204 �`\306 \210i \\\262\211b\210\307c\210j\266\310\205&�\311\312\205,�\313\2052�\314R\303#\211\204W�\203P�\315 \210\316\210?\205\276�\315 \210\316\207\317`\"\210\303\207\320c\210\303\211\203\244�\310\321!\210\203q�`\262\322c\210\202\206�\323c\210\310\324\303\325#\204\200�\326\327!\210`\262\322c\210\330 \210`\262\307c\210j\210\310\331\205\232�\313\314Q\320\325#\262\202\\�\211`|\210b\210\332c\210\303\210\n\203\273�\333`\334#\210\266\325\207" [vhdl-argument-list-indent vhdl-basic-offset vhdl-auto-align nil vhdl-insert-keyword "GENERIC (" back-to-indentation "\n" vhdl-template-field "[" "name" "s" "]" vhdl-line-kill-entire 0 vhdl-template-undo " : " "type" ";" " := " "[value]" t delete-char -4 vhdl-comment-insert-inline "[name" ")" vhdl-align-region-groups 1] 11 (#$ . 345698)])#@58 Read from user a port spec argument list. (fn OPTIONAL) (defalias 'vhdl-template-port-list #[257 "`\303\211\211\304\305!\210i\262\204\"�`\306 \210i \\\262\211b\210\307c\210j\266\310\311!\203/�\312\313\314\315#\262\312\2055�\316\317\205<�\320Q\303#\262\204c�\203\\�\321 \210\322\210?\205\343�\321 \210\322\207\323`\"\210\303\207\324c\210\303\211\203\310�\203w�\226\325\232\203�\312\326\314\"\210\202\214�\226\327\232\203\214�\312\330\314\315#\210\312\203\234�\226\331\232\203\234�\332\202\235�\333!\210`\262\334c\210\335 \210`\262\307c\210j\210\310\311!\203\276�\312\313\314\315#\262\312\336\324\315#\262\202h�\211`|\210b\210\337c\210\303\210\n\203\340�\340\341#\210\266\315\207" [vhdl-argument-list-indent vhdl-basic-offset vhdl-auto-align nil vhdl-insert-keyword "PORT (" back-to-indentation "\n" vhdl-standard-p ams vhdl-template-field "[SIGNAL | TERMINAL | QUANTITY]" " " t "[" "names" "]" vhdl-line-kill-entire 0 vhdl-template-undo " : " "SIGNAL" "IN | OUT | INOUT" "QUANTITY" "[IN | OUT]" "TERMINAL" "nature" "type" ";" vhdl-comment-insert-inline "[names]" ")" vhdl-align-region-groups 1] 11 (#$ . 346665)])#@55 Insert body for generate template. (fn MARGIN LABEL) (defalias 'vhdl-template-generate-body #[514 "\301\302!\210\303c\210j\210\301\304!\210\211\305\261\210\306\210\\j\207" [vhdl-basic-offset vhdl-insert-keyword " GENERATE" "\n\n" "END GENERATE " ";" 0] 4 (#$ . 347820)])#@36 Insert date in appropriate format. (defalias 'vhdl-template-insert-date #[0 "\301\267\202�\302\303\304\"\202�\302\305\304\"\202�\302\306\304\"\202�\302\304\"c\207" [vhdl-date-format #s(hash-table size 3 test eq rehash-size 1.5 rehash-threshold 0.8125 purecopy t data (american 6 european 13 scientific 20)) format-time-string "%m/%d/%Y" nil "%d.%m.%Y" "%Y/%m/%d"] 3 (#$ . 348102) nil])#@132 Expand abbreviations and self-insert space(s), do `indent-new-comment-line' if in comment and past end-comment-column. (fn COUNT) (defalias 'vhdl-electric-space #[257 "\303 \203-�\304!\210i\305\\Y\203\"�\306u\210\307\310x\210\311 \210\307\310w\210\312u\207iY\203+�\311 \207\310\207h\313Y\2039�h\314X\204E�h\315Y\203d�h\316X\203d�\317\320 p\321\322#\216\323\n!\210\324 \204]�\325\306!\210*\266\304!\207\304!\207" [end-comment-column case-fold-search vhdl-mode-ext-syntax-table vhdl-in-comment-p self-insert-command 2 -1 "^ \n \f" nil indent-new-comment-line 1 97 122 65 90 t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table expand-abbrev vhdl-fix-case-word] 7 (#$ . 348500) "p"])#@442 Prompt for string and insert it in buffer with optional FOLLOW-STRING. If OPTIONAL is nil, the prompt is left if an empty string is inserted. If an empty string is inserted, return nil and call `vhdl-template-undo' for the region between BEGIN and END. IS-STRING indicates whether a string with double-quotes is to be inserted. DEFAULT specifies a default string. (fn PROMPT &optional FOLLOW-STRING OPTIONAL BEGIN END IS-STRING DEFAULT) (defalias 'vhdl-template-field #[1793 "`\306\307 \310\261\210\3111!�\312 \313P\203�\314\202�#0\2028�\210\2036�\2036�\2036�\315 \210\316\2028�\317 \262\211\316\232\203E�\203I�`|\210\211\316\232\203g�\203g�\203g�\203g�\320\"\210\321\322!\210\211\316\232\204\232�\211c\210\323` \n$\210\323` \f$\210\323` \324P$\210\323`$\210\323`$\210\211\316\232\203\245�\204\255�\206\253�\316c\210\211\316\232?\205\265�\211\207" [vhdl-minibuffer-local-map vhdl-upper-case-keywords vhdl-keywords-regexp vhdl-upper-case-types vhdl-types-regexp vhdl-upper-case-attributes nil "<" ">" (quit) read-from-minibuffer ": " ("\"\"" . 2) beep "" keyboard-quit vhdl-template-undo message "Template aborted" vhdl-fix-case-region-1 "'" vhdl-attributes-regexp vhdl-upper-case-enum-values vhdl-enum-values-regexp vhdl-upper-case-constants vhdl-constants-regexp] 15 (#$ . 349249)])#@72 Query a decision from the user. (fn STRING PROMPT &optional OPTIONAL) (defalias 'vhdl-decision-query #[770 "`\203 �\300\301P!\210\302\303\206�\304\"\210\305 `|\210\203/�\211\306=\203/�\301c\210\307 \210\310\311\312\"\207\207" [vhdl-insert-keyword " " message "%s" "" read-char 13 unexpand-abbrev throw abort "ERROR: Template aborted"] 8 (#$ . 350585)])#@47 Insert KEYWORD and adjust case. (fn KEYWORD) (defalias 'vhdl-insert-keyword #[257 "\203 �\211\226\202 �\211\227c\207" [vhdl-upper-case-keywords] 2 (#$ . 350951)])#@39 Adjust case of KEYWORD. (fn KEYWORD) (defalias 'vhdl-case-keyword #[257 "\203�\211\226\207\211\227\207" [vhdl-upper-case-keywords] 2 (#$ . 351121)])#@47 Adjust case of following NUM words. (fn NUM) (defalias 'vhdl-case-word #[257 "\203�\301!\207\302!\207" [vhdl-upper-case-keywords upcase-word downcase-word] 3 (#$ . 351278)])#@156 If preceding character is part of a word or a paren then hippie-expand, else insert tab (used for word completion in VHDL minibuffer). (fn &optional ARG) (defalias 'vhdl-minibuffer-tab #[256 "hz\304U\203�?\305\306\301!\203� \206�\307\310!+\207h\311U\204)�h\312U\2033�?\305\313!*\207\314 \207" [vhdl-word-completion-case-sensitive hippie-expand-only-buffers case-replace case-fold-search 119 nil boundp (vhdl-mode) vhdl-expand-abbrev 40 41 vhdl-expand-paren insert-tab] 5 (#$ . 351463) "P"])#@55 Search for left out template prompts and query again. (defalias 'vhdl-template-search-prompt #[0 "\303\304 p\305\306#\216\307 !\210\310\311\n\312Q\313\303#\204%�\314\311\n\312Q\313\303#\2051�\315\316!\317\320!\210\321!\262)\266\202)\207" [case-fold-search vhdl-mode-ext-syntax-table vhdl-template-prompt-syntax t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table re-search-forward "<\\(" "\\)>" nil re-search-backward match-string 1 replace-match "" vhdl-template-field] 6 (#$ . 351972) nil])#@87 Undo aborted template by deleting region and unexpanding the keyword. (fn BEGIN END) (defalias 'vhdl-template-undo #[514 "\203�\211b\210\301c\210|\210\302 \207|\207" [vhdl-template-invoked-by-hook " " unexpand-abbrev] 4 (#$ . 352527)])#@81 Insert STRING or file contents if STRING is an existing file name. (fn STRING) (defalias 'vhdl-insert-string-or-file #[257 "\211\300\232?\205%�\301\302\"\210\303\304\305\"!\306!\203!�\307!A@u\202#�c\262\207" ["" string-match "^\\([^\n]+\\)" vhdl-resolve-env-variable match-string 1 file-exists-p insert-file-contents] 5 (#$ . 352775)])#@54 Move cursor to the beginning of the enclosing block. (defalias 'vhdl-beginning-of-block #[0 "\302\303\304 p\305\306#\216\307 !\210\212\310 \210\311\312\302\303#\211\262\203o�\313\314!\203Q�\315 \305\316\"\216\212\314\225b\210\317\320!\210\321 \210\322\323!\203A�\324 \210\325\326\302\303#)\210\313\320!)\262\204�\313\327!\203o�\315 \305\330\"\216\212\331 \210\310 \210\322\332!*?\262\204�\313\333!\203{�\334 \210\202�+\266\211\205\204�\211b\207" [case-fold-search vhdl-mode-ext-syntax-table nil t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table beginning-of-line re-search-backward "^\\s-*\\(\\(end\\)\\|\\(\\(impure\\|pure\\)[ \n \f]+\\)?\\(function\\|procedure\\)\\|\\(for\\)\\|\\(architecture\\|component\\|configuration\\|context\\|entity\\|package\\(\\s-+body\\)?\\|type[ \n \f]+\\w+[ \n \f]+is[ \n \f]+\\(record\\|protected\\(\\s-+body\\)?\\)\\|units\\)\\|\\(\\w+[ \n \f]*:[ \n \f]*\\)?\\(postponed[ \n \f]+\\)?\\(block\\|case\\|for\\|if\\|procedural\\|process\\|while\\|loop\\)\\)\\>" match-string 5 match-data #[0 "\301\300\302\"\207" [V0 set-match-data t] 3] forward-word-strictly 1 vhdl-forward-syntactic-ws looking-at "(" forward-sexp re-search-forward "\\<is\\>\\|\\(;\\)" 6 #[0 "\301\300\302\"\207" [V0 set-match-data t] 3] vhdl-end-of-block "^\\s-*end\\s-+\\(for\\|generate\\|loop\\)\\>" 2 vhdl-beginning-of-block] 8 (#$ . 353123)])#@48 Move cursor to the end of the enclosing block. (defalias 'vhdl-end-of-block #[0 "\302\303\304 p\305\306#\216\307 !\210\212\302\210\310\311\302\303#\211\262\203[�\312\313!\203=�\314 \305\315\"\216\212\310\316\302\303#)\210\312\317!)\262\204�\312\320!\203[�\314 \305\321\"\216\212\322 \210\323 \210\324\325!*?\262\204�\312\326!\204g�\322 \210\202�+\266\211\205p�\211b\207" [case-fold-search vhdl-mode-ext-syntax-table nil t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table re-search-forward "^\\s-*\\(\\(end\\)\\|\\(\\(impure\\|pure\\)[ \n \f]+\\)?\\(function\\|procedure\\)\\|\\(for\\)\\|\\(architecture\\|component\\|configuration\\|context\\|entity\\|package\\(\\s-+body\\)?\\|type[ \n \f]+\\w+[ \n \f]+is[ \n \f]+\\(record\\|protected\\(\\s-+body\\)?\\)\\|units\\)\\|\\(\\w+[ \n \f]*:[ \n \f]*\\)?\\(postponed[ \n \f]+\\)?\\(block\\|case\\|for\\|if\\|procedural\\|process\\|while\\|loop\\)\\)\\>" match-string 5 match-data #[0 "\301\300\302\"\207" [V0 set-match-data t] 3] "\\<is\\>\\|\\(;\\)" 1 6 #[0 "\301\300\302\"\207" [V0 set-match-data t] 3] vhdl-end-of-block beginning-of-line looking-at "^\\s-*end\\s-+\\(for\\|generate\\|loop\\)\\>" 2] 8 (#$ . 354548)])#@53 Check if point is within sequential statement part. (defalias 'vhdl-sequential-statement-p #[0 "`\212\302\303 p\304\305#\216\306 !\210\307\310\311\302#\205(�\312 \210`W\205(�\313 \210\314\315!)\266\202*\207" [case-fold-search vhdl-mode-ext-syntax-table t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table re-search-backward "^\\s-*begin\\>" nil vhdl-end-of-block vhdl-beginning-of-block looking-at "^\\s-*\\(\\(\\w+[ \n \f]+\\)?\\(function\\|procedure\\)\\|\\(\\w+[ \n \f]*:[ \n \f]*\\)?\\(\\w+[ \n \f]+\\)?\\(procedural\\|process\\)\\)\\>"] 7 (#$ . 355791)])#@35 Check if within an argument list. (defalias 'vhdl-in-argument-list-p #[0 "\212\302\303 p\304\305#\216\306 !\210\307\310\311\312\313 @@\"\"\206#�\314 \210\315\316!)\266\202*\207" [case-fold-search vhdl-mode-ext-syntax-table t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table string-match "arglist" format "%s" vhdl-get-syntactic-context beginning-of-line looking-at "^\\s-*\\(generic\\|port\\|\\(\\(impure\\|pure\\)\\s-+\\|\\)function\\|procedure\\)\\>\\s-*\\(\\w+\\s-*\\)?("] 7 (#$ . 356416)])#@125 Do function, if syntax says abbrev is a keyword, invoked by hooked abbrev, but not if inside a comment or quote. (fn FUNC) (defalias 'vhdl-hooked-abbrev #[257 "\306 \204�\212\307\310!\210\311\312!\205�\311\313!?)\203*�\314c\210\315 \210\316\317!\210\320\317!\210\321\317!\207\204@�\314c\210\315 \210\316\317!\210\320\317!\210\321\317!\207 \310\322\3232L� 0\211;\203V�\324\325\"\210\210\211\326U\203_�`\327\330!\203l�\330\321\310\"\202s�\331\332! B\211*\207" [vhdl-electric-mode vhdl-last-input-event vhdl-template-invoked-by-hook abbrev-mode abbrev-start-location unread-command-events vhdl-in-literal forward-word-strictly -1 looking-at "\\<end\\>" "\\<end;" " " unexpand-abbrev backward-word-strictly 1 vhdl-case-word delete-char t abort message "%s" 45 fboundp enqueue-eval-event vhdl-character-to-event 127] 6 (#$ . 356972)]) (defalias 'vhdl-template-alias-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-alias] 2]) (defalias 'vhdl-template-architecture-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-architecture] 2]) (defalias 'vhdl-template-assert-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-assert] 2]) (defalias 'vhdl-template-attribute-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-attribute] 2]) (defalias 'vhdl-template-block-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-block] 2]) (defalias 'vhdl-template-break-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-break] 2]) (defalias 'vhdl-template-case-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-case] 2]) (defalias 'vhdl-template-component-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-component] 2]) (defalias 'vhdl-template-instance-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-instance] 2]) (defalias 'vhdl-template-conditional-signal-asst-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-conditional-signal-asst] 2]) (defalias 'vhdl-template-configuration-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-configuration] 2]) (defalias 'vhdl-template-constant-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-constant] 2]) (defalias 'vhdl-template-context-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-context] 2]) (defalias 'vhdl-template-disconnect-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-disconnect] 2]) (defalias 'vhdl-template-display-comment-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-comment-display] 2]) (defalias 'vhdl-template-else-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-else] 2]) (defalias 'vhdl-template-elsif-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-elsif] 2]) (defalias 'vhdl-template-entity-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-entity] 2]) (defalias 'vhdl-template-exit-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-exit] 2]) (defalias 'vhdl-template-file-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-file] 2]) (defalias 'vhdl-template-for-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-for] 2]) (defalias 'vhdl-template-function-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-function] 2]) (defalias 'vhdl-template-generic-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-generic] 2]) (defalias 'vhdl-template-group-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-group] 2]) (defalias 'vhdl-template-library-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-library] 2]) (defalias 'vhdl-template-limit-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-limit] 2]) (defalias 'vhdl-template-if-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-if] 2]) (defalias 'vhdl-template-bare-loop-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-bare-loop] 2]) (defalias 'vhdl-template-map-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-map] 2]) (defalias 'vhdl-template-nature-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-nature] 2]) (defalias 'vhdl-template-next-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-next] 2]) (defalias 'vhdl-template-others-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-others] 2]) (defalias 'vhdl-template-package-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-package] 2]) (defalias 'vhdl-template-port-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-port] 2]) (defalias 'vhdl-template-procedural-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-procedural] 2]) (defalias 'vhdl-template-procedure-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-procedure] 2]) (defalias 'vhdl-template-process-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-process] 2]) (defalias 'vhdl-template-quantity-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-quantity] 2]) (defalias 'vhdl-template-report-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-report] 2]) (defalias 'vhdl-template-return-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-return] 2]) (defalias 'vhdl-template-selected-signal-asst-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-selected-signal-asst] 2]) (defalias 'vhdl-template-signal-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-signal] 2]) (defalias 'vhdl-template-subnature-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-subnature] 2]) (defalias 'vhdl-template-subtype-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-subtype] 2]) (defalias 'vhdl-template-terminal-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-terminal] 2]) (defalias 'vhdl-template-type-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-type] 2]) (defalias 'vhdl-template-use-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-use] 2]) (defalias 'vhdl-template-variable-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-variable] 2]) (defalias 'vhdl-template-wait-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-wait] 2]) (defalias 'vhdl-template-when-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-when] 2]) (defalias 'vhdl-template-while-loop-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-while-loop] 2]) (defalias 'vhdl-template-with-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-with] 2]) (defalias 'vhdl-template-and-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-and] 2]) (defalias 'vhdl-template-or-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-or] 2]) (defalias 'vhdl-template-nand-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-nand] 2]) (defalias 'vhdl-template-nor-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-nor] 2]) (defalias 'vhdl-template-xor-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-xor] 2]) (defalias 'vhdl-template-xnor-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-xnor] 2]) (defalias 'vhdl-template-not-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-not] 2]) (defalias 'vhdl-template-default-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-default] 2]) (defalias 'vhdl-template-default-indent-hook #[0 "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-default-indent] 2])#@62 Insert the built-in construct template with NAME. (fn NAME) (defalias 'vhdl-template-insert-construct #[257 "\301\302\"A@!\207" [vhdl-template-construct-alist vhdl-template-insert-fun assoc] 5 (#$ . 364187) (byte-code "\302\303\304 \305\302$)C\207" [completion-ignore-case vhdl-template-construct-alist t completing-read "Construct name: " nil] 5)])#@60 Insert the built-in package template with NAME. (fn NAME) (defalias 'vhdl-template-insert-package #[257 "\301\302\"A@!\207" [vhdl-template-package-alist vhdl-template-insert-fun assoc] 5 (#$ . 364546) (byte-code "\302\303\304 \305\302$)C\207" [completion-ignore-case vhdl-template-package-alist t completing-read "Package name: " nil] 5)])#@62 Insert the built-in directive template with NAME. (fn NAME) (defalias 'vhdl-template-insert-directive #[257 "\301\302\"A@!\207" [vhdl-template-directive-alist vhdl-template-insert-fun assoc] 5 (#$ . 364895) (byte-code "\302\303\304 \305\302$)C\207" [completion-ignore-case vhdl-template-directive-alist t completing-read "Directive name: " nil] 5)])#@51 Call FUN to insert a built-in template. (fn FUN) (defalias 'vhdl-template-insert-fun #[257 "\3002 �\211\205\n�\211 0\211;\205�\301\302\"\207" [abort message "%s"] 5 (#$ . 365254)])#@62 Insert the user model with name MODEL-NAME. (fn MODEL-NAME) (defalias 'vhdl-model-insert #[257 "\306 \210\307 \310 \311\211\211\211\211\312\313 p\314\315#\216\316 !\210\317\n\n\"\211\262\205\361�\320 \210\321 \210b\210\322A@!\210\307 \262b\210\320 \210`W\203[�\323\324!\204T�\325\326 \"\210\320\327!\210\202B�b\210 \330\232\204t�\331\332\312#\203t�\333 !\210\202e�b\210\f\330\232\204\215�\331\334\312#\203\215�\333\f!\210\202~�\335 \311\312$\210b\210\331\336 \337Q\312#\203\335�\340\341!\342\232\204\231�\341\224\262\340\341!\262\333\330!\210\343\311\312#\262\331\336\337Q\312#\203\327�\333\206\322�\330!\210\202\300�b\210\202\231�b\210\331\344\312#\203\357�\333\330!\202\361�b)\266\202)\207" [case-fold-search vhdl-mode-ext-syntax-table vhdl-model-alist vhdl-clock-name vhdl-reset-name vhdl-template-prompt-syntax indent-according-to-mode point-marker current-indentation nil t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table assoc beginning-of-line delete-horizontal-space vhdl-insert-string-or-file looking-at "^$" insert-char 32 2 "" re-search-forward "<clock>" replace-match "<reset>" vhdl-template-replace-header-keywords "<\\(" "\\)>" match-string 1 "cursor" vhdl-template-field "<cursor>"] 15 (#$ . 365443) (byte-code "\302\303\304 \")C\207" [completion-ignore-case vhdl-model-alist t completing-read "Model name: "] 3)])#@49 Define help and hook functions for user models. (defalias 'vhdl-model-defun #[0 "\301\211\205H�@@\262\302\303\304\305\"\301\306\307Q\310\311D\257!\210\312@8\262\211\313\232\204A�\302\303\304\305\314#\301\315\316\304\305 \"DDF!\210A\262\202�\207" [vhdl-model-alist nil eval defun vhdl-function-name "vhdl-model" "Insert model for \"" "\"." (interactive) vhdl-model-insert 3 "" "hook" vhdl-hooked-abbrev quote] 12 (#$ . 366872)]) (vhdl-model-defun)#@40 Variable to hold last port map parsed. (defvar vhdl-port-list nil (#$ . 367341))#@99 Check that the text following point matches the regexp in STRING. (fn STRING &optional OPTIONAL) (defalias 'vhdl-parse-string #[513 "\300!\203�\301\225b\210\302 \203�\303\210`\207\211\204#�\304\305\306\307\310 #\"\210\303\207" [looking-at 0 vhdl-in-literal nil throw parse format "ERROR: Syntax error near line %s, expecting \"%s\"" vhdl-current-line] 8 (#$ . 367427)])#@110 Replace STRING from car of REGEXP-CONS to cdr of REGEXP-CONS. (fn REGEXP-CONS STRING &optional ADJUST-CASE) (defalias 'vhdl-replace-string #[770 "\303\304 p\305\306#\216\307 !\210\310@\"\2034�\203)�\n\311A\303\312$!\2025�\311A\303\312$\2025�)\266\202)\207" [case-fold-search vhdl-mode-ext-syntax-table vhdl-file-name-case t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table string-match replace-match nil] 11 (#$ . 367811)])#@56 Parse comment and empty lines between groups of lines. (defalias 'vhdl-parse-group-comment #[0 "`\300\301d!\210\302`\"\262\303 \210\304\305\"\203&�\211\306\307\224O\307\225\300OP\262\202�\211\310\232\204:�\211\306\307O\311\232\203:�\211\307\300O\207\207" [nil vhdl-forward-comment buffer-substring-no-properties vhdl-forward-syntactic-ws string-match "^\\(\\s-+\\)" 0 1 "" "\n"] 6 (#$ . 368308)])#@100 Paste comment and empty lines from STRING between groups of lines with INDENT. (fn STRING INDENT) (defalias 'vhdl-paste-group-comment #[514 "\300 \301V\203#�\302\303\"\203#�\301\304\224O\305\306\"\304\224\307OQ\262\202�\310 \210c\210\211b\207" [point-marker 0 string-match "^\\(--\\)" 1 make-string 32 nil beginning-of-line] 8 (#$ . 368717)])#@46 Indicates whether a port has been flattened. (defvar vhdl-port-flattened nil (#$ . 369074))#@203 Flatten port list so that only one generic/port exists per line. This operation is performed on an internally stored port and is only reflected in a subsequent paste operation. (fn &optional AS-ALIST) (defalias 'vhdl-port-flatten #[256 "\204�\302\303!\207\304\305!\210@CA\306\211\211\211\211A\203h�@\262\306\262\203Y�@\262@\262\211\203R�\203<�\211@\202?�\211@CAB\262\307C\"\262\211A\262\202.�A\262\202\"�A\262\307C\"\262\202�\307C\"\310\304\311!\207" [vhdl-port-list vhdl-port-flattened error "ERROR: No port has been read" message "Flattening port for next paste..." nil append t "Flattening port for next paste...done"] 11 (#$ . 369172) nil])#@49 Indicates whether port directions are reversed. (defvar vhdl-port-reversed-direction nil (#$ . 369860))#@170 Reverse direction for all ports (useful in testbenches). This operation is performed on an internally stored port and is only reflected in a subsequent paste operation. (defalias 'vhdl-port-reverse-direction #[0 "\204�\302\303!\207\304\305!\210\3068\307\211\203@�@AA\262@\262\310\267\2026�\311\2027�\312\2027�\313\2027�\314\2027�\240\210A\262\202� ?\304\315!\207" [vhdl-port-list vhdl-port-reversed-direction error "ERROR: No port has been read" message "Reversing port directions for next paste..." 2 nil #s(hash-table size 4 test equal rehash-size 1.5 rehash-threshold 0.8125 purecopy t data ("in" 38 "IN" 42 "out" 46 "OUT" 50)) "out" "OUT" "in" "IN" "Reversing port directions for next paste...done"] 6 (#$ . 369970) nil])#@75 Get generic and port information from an entity or component declaration. (defalias 'vhdl-port-copy #[0 "\212\305\211\211\211\211\211\211\211\211\211\211\211\211\211\306\307 p\310\311#\216\312 !\210\3132\203\305\210\314\315\305\306#\2036�\316\317!\226\320\232\203;�\321\313\322\"\210\323\317!\227\262\324\317!\210\325\326!\210\323\317!\262 \327\330#\210\331 \210\325\332\306\"\203\211\333 \262\325\334\306\"\262\204\211\325\335!\210\323\317!C\262\325\336\306\"\203\215�\337\323\317!C\"\262\202y�\325\340!\210\323\317!\262\341 \203\250�\325\342!\205\245�\323\343!P\262\305\262\344\345!\203\311�\346`\347 \210`\"\325\350\306\"\205\303�\323\317!Q\262\202\253�\203\343�\351\352\"\203\343�\353\224\305O\262\343\317\224O\262\351\354\"\210\343\317\225O\262\305\262\325\355\306\"\203!\325\356!\210\323\317!\262\344\345!\203!\346`\347 \210`\"\325\356\306\"\205\323\317!Q\262\202\203>\351\352\"\203>\353\224\305O\262\343\317\224O\262\331 \210\357\305w\210\204R\325\360\306\"\205P\323\317!\262\331 \210\325\361\306\"\262\325\362!\210\204o\325\360\306\"\205m\323\317!\262\337\f \257C\"\262\f\333 \262\202j�\325\363\306\"\203u\333 \262\325\334\306\"\262\204u\325\364\306\"\205\251\323\317!\262 \325\335!\210\323\317!C\262\325\336\306\"\203\311\337\323\317!C\"\262\202\265\325\365!\210\325\366\306\"\205\327\323\317!\262\325\367!\210\323\317!\262\341 \203\364\325\342!\205\361\323\343!P\262\305\262\344\345!\203\346`\347 \210`\"\325\356\306\"\205\323\317!Q\262\202\367\203/\351\352\"\203/\353\224\305O\262\343\317\224O\262\351\354\"\210\343\317\225O\262\331 \210\325\361\306\"\262\325\362!\210\204Y\325\360\306\"\205W\323\317!\262\337   \n\n  \257C\"\262 \333 \262\202\232\370 \262\n\327\371#\210\3050*\262\266 \203\226\372!\266\216\202\247\n\n\n\nF\305\211\211\266\216)\207" [case-fold-search vhdl-mode-ext-syntax-table vhdl-port-list vhdl-port-reversed-direction vhdl-port-flattened nil t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table parse re-search-backward "^\\s-*\\(component\\|entity\\|end\\)\\>" match-string 1 "END" throw "ERROR: Not within an entity or component declaration" match-string-no-properties forward-word-strictly vhdl-parse-string "\\s-+\\(\\w+\\)\\(\\s-+is\\>\\)?" message "Reading port of %s \"%s\"..." vhdl-forward-syntactic-ws "generic[ \n \f]*(" vhdl-parse-group-comment ")[ \n \f]*;[ \n \f]*" "\\(\\\\[^\\]+\\\\\\|\\w+\\)[ \n \f]*" ",[ \n \f]*\\(\\\\[^\\]+\\\\\\|\\w+\\)[ \n \f]*" append ":[ \n \f]*\\([^():;\n]+\\)" vhdl-in-comment-p ".*" 0 looking-at "(" buffer-substring-no-properties forward-sexp "\\([^():;\n]*\\)" string-match "\\(\\s-*--\\s-*\\)\\(.*\\)" 2 "\\(\\(\\s-*\\S-+\\)+\\)\\s-*" ":=[ \n \f]*" "\\([^();\n]*\\)" " " "--\\s-*\\([^\n]*\\)" ")" "\\s-*;\\s-*" "port[ \n \f]*(" "\\<\\(signal\\|quantity\\|terminal\\)\\>[ \n \f]*" ":[ \n \f]*" "\\<\\(in\\|out\\|inout\\|buffer\\|linkage\\)\\>[ \n \f]+" "\\([^();\n]+\\)" vhdl-scan-context-clause "Reading port of %s \"%s\"...done" error] 25 (#$ . 370717) nil])#@59 Paste a context clause. (fn &optional EXCLUDE-PACK-NAME) (defalias 'vhdl-port-paste-context-clause #[256 "\3018\302\205<�@\262\203�\211A\227\227\232\2045�\212\303\304@\305A\306\260\302\307#)\2045�\310@A\"\210\311c\210A\262\202�\207" [vhdl-port-list 3 nil re-search-backward "^\\s-*use\\s-+" "." "\\>" t vhdl-template-standard-package "\n"] 9 (#$ . 373877)])#@49 Paste a generic clause. (fn &optional NO-INIT) (defalias 'vhdl-port-paste-generic #[256 "\306 A@\307\211\211\211\205\242�`\262\310\311!\210 \204 �\312c\210\n\\j\210i\262\203\230�@\262 \313>\2038�\314\3158\"\210\211@\262\203R�@c\210A\262\203<�\316c\210\202<�\317A@\261\210\204k�\3208\203k�\321\3208\261\210A\204s�\322c\210\323c\210\f\203\207�\3248\203\207�\325\3248\326\"\210A\262\203#�\312c\210j\210\202#� \205\242�\327`\330\326$\207" [vhdl-port-list vhdl-argument-list-indent vhdl-basic-offset vhdl-include-group-comments vhdl-include-port-comments vhdl-auto-align current-indentation nil vhdl-insert-keyword "GENERIC (" "\n" (decl always) vhdl-paste-group-comment 4 ", " " : " 2 " := " ")" ";" 3 vhdl-comment-insert-inline t vhdl-align-region-groups 1] 12 (#$ . 374256)])#@22 Paste a port clause. (defalias 'vhdl-port-paste-port #[0 "\306 \3078\310\211\211\211\205\252�`\262\311\312!\210 \204 �\313c\210\n\\j\210i\262\203\241�@\262 \314>\2038�\315\3168\"\210\211A@\203E�\211A@\317\261\210\211@\262\203_�@c\210A\262\203I�\320c\210\202I�\321c\210\3078\203o�\3078\317\261\210\3228c\210A\204|�\323c\210\324c\210\f\203\220�\3258\203\220�\326\3258\327\"\210A\262\203#�\313c\210j\210\202#� \205\252�\330`\331#\207" [vhdl-port-list vhdl-argument-list-indent vhdl-basic-offset vhdl-include-group-comments vhdl-include-port-comments vhdl-auto-align current-indentation 2 nil vhdl-insert-keyword "PORT (" "\n" (decl always) vhdl-paste-group-comment 5 " " ", " " : " 3 ")" ";" 4 vhdl-comment-insert-inline t vhdl-align-region-groups 1] 10 (#$ . 375067)])#@77 Paste as an entity or component declaration. (fn KIND &optional NO-INDENT) (defalias 'vhdl-port-paste-declaration #[513 "\211\204�\303 \210\304 @\305\306=\203�\307\202�\310!\210\211c\210\306=\204(�\311\312!\204,�\305\313!\210A@\203O�\314c\210 \315>\203D�\306=\203D�\314c\210\n\\j\210\316\317=!\210\3208\203l�\314c\210 \321>\203g�\306=\203g�\314c\210\n\\j\210\322 \210\314c\210 \323>\203\201�\306=\203\201�\314c\210j\210\305\324!\210\306=\203\240�\311\312!\204\230�\305\325!\210\326\261\210\202\257�\305\327!\210\311\312!\204\257�\326\261\210\330c\207" [vhdl-port-list vhdl-insert-empty-lines vhdl-basic-offset indent-according-to-mode current-indentation vhdl-insert-keyword entity "ENTITY " "COMPONENT " vhdl-standard-p 87 " IS" "\n" (unit all) vhdl-port-paste-generic component 2 (unit all) vhdl-port-paste-port (unit all) "END" " ENTITY" " " " COMPONENT" ";"] 7 (#$ . 375868)])#@59 Paste as an entity declaration. (fn &optional NO-INDENT) (defalias 'vhdl-port-paste-entity #[256 "\204�\301\302!\207\303\304@\"\210\305\306\"\210\303\307@\"\207" [vhdl-port-list error "ERROR: No port read" message "Pasting port as entity \"%s\"..." vhdl-port-paste-declaration entity "Pasting port as entity \"%s\"...done"] 4 (#$ . 376775) nil])#@61 Paste as a component declaration. (fn &optional NO-INDENT) (defalias 'vhdl-port-paste-component #[256 "\204�\301\302!\207\303\304@\"\210\305\306\"\210\303\307@\"\207" [vhdl-port-list error "ERROR: No port read" message "Pasting port as component \"%s\"..." vhdl-port-paste-declaration component "Pasting port as component \"%s\"...done"] 4 (#$ . 377133) nil])#@64 Paste as a generic map. (fn &optional SECONDARY NO-CONSTANTS) (defalias 'vhdl-port-paste-generic-map #[512 "\204�\306 \210\307 \310\211\211A@\211\205\374�`\262\311\312!\210 \204[�\211\205\374�\203-�\211@@@\2025�\313@8\2065�\314c\210\211A\262\211\203C�\315\202D�\316c\210\211\204�\203�\3138\204�\317c\210\202�\n\204g�\320c\210 \\j\210i\262\211\203\361�\211@\262\f\321=\203�\322\3238\"\210@@\324\203\221�\325 @@\"\202\230�\3138\206\230�\326\261\210\211A\262\211\203\247�\327\202\250�\316c\210\211\204\274�\203\274�\3138\204\274�\317c\210\204\314� \203\344�\3308\203\344�\331\205\330�\332A@\333Q \205\340�\3308P\334\"\210\211\203j�\320c\210j\210\202j�!\205\374�\335`\336\334$\207" [vhdl-port-list vhdl-association-list-with-formals vhdl-argument-list-indent vhdl-basic-offset vhdl-include-group-comments vhdl-actual-generic-name indent-according-to-mode current-indentation nil vhdl-insert-keyword "GENERIC MAP (" 2 " " ", " ")" ";" "\n" always vhdl-paste-group-comment 4 " => " vhdl-replace-string "" "," 3 vhdl-comment-insert-inline "[" "] " t vhdl-align-region-groups 1 vhdl-include-type-comments vhdl-include-port-comments vhdl-auto-align] 12 (#$ . 377505) nil])#@22 Paste as a port map. (defalias 'vhdl-port-paste-port-map #[0 "\306 \307\211\211\3108\211\205\377�`\262\311\312!\210 \2046�\211\205\377�\313\n@@@\"c\210\211A\262\211\2030�\314\2021�\315c\210\202� \204B�\316c\210\f\\j\210i\262\211\203\365�\211@\262 \317=\203Z�\320\3218\"\210@@\322\261\210\313\n@@\"c\210\211A\262\211\203u�\323\202v�\324c\210\"\203\203�\3108\204\223�#\204\223�$\203\350�\3258\203\350�\326\"\203\260�#\203\260�\327\330\331\3108\332P\"\3338\334R\202\334�\"\203\310�\3108\203\310�\330\335\327\3108\334Q\"\202\334�\"\203\321�\336\202\334�#\205\334�\327\3338\334Q$\205\344�\3258P\337\"\210\211\203E�\316c\210j\210\202E�%\205\377�\340`\341#\207" [vhdl-port-list vhdl-association-list-with-formals vhdl-actual-port-name vhdl-argument-list-indent vhdl-basic-offset vhdl-include-group-comments current-indentation nil 2 vhdl-insert-keyword "PORT MAP (" vhdl-replace-string ", " ")" "\n" always vhdl-paste-group-comment 5 " => " "," ");" 4 vhdl-comment-insert-inline "[" format "%-4s" " " 3 "] " "%-6s" " " t vhdl-align-region-groups 1 vhdl-include-direction-comments vhdl-include-type-comments vhdl-include-port-comments vhdl-auto-align] 11 (#$ . 378717)])#@65 Paste as an instantiation. (fn &optional NAME NO-INDENT TITLE) (defalias 'vhdl-port-paste-instance #[768 "\204�\303\304!\207\305 \210\204�\306 \210\307 \203�c\210\202d� A\310\232\203.�\311\312!\262\202d�\313\314 A\"\203]�\315\212\316\317 @\"\"\262eb\210\320\321\322#)\203V�\211T\262\2027�c\266\202d�\317 @\"c\210\323\324\"\210\325c\210\203�\212\326 \210\nj\210\327\330\261)\210\331 \204\213�@c\210\202\227�\332\333!\210\334 \335@\261\210A@\203\252�\336c\210\211\n\\j\210\337\322\211\"\210\3408\203\273�\336c\210\211\n\\j\210\341 \210A@\204\312�\3408\204\312�\342c\210\323\343\"\266\211\211\207" [vhdl-port-list vhdl-instance-name vhdl-basic-offset error "ERROR: No port read" vhdl-port-flatten indent-according-to-mode current-indentation "" vhdl-template-field "instance name" string-match "%d" 1 format vhdl-replace-string vhdl-re-search-forward nil t message "Pasting port as instantiation \"%s\"..." ": " beginning-of-line "-- instance \"" "\"\n" vhdl-use-direct-instantiation vhdl-insert-keyword "ENTITY " vhdl-work-library "." "\n" vhdl-port-paste-generic-map 2 vhdl-port-paste-port-map ";" "Pasting port as instantiation \"%s\"...done"] 10 (#$ . 379926) nil])#@56 Paste generics as constants. (fn &optional NO-INDENT) (defalias 'vhdl-port-paste-constants #[256 "\204�\305\306!\207\307\310!\210\311 \210\204�\312 \210\313 \314\211\211A@\211\203\222�`\262\211\203\210�\211@\262 \315>\203<�\316\3178\"\210\320\321!\210@\262\203&�\322\n@\"c\210\323A@\261\210\3248\203c�\325\3248\261\210\326c\210 \203w�\3278\203w�\330\3278\331\"\210\211A\262\211\203&�\332c\210j\210\202&�\f\203\222�\333`\334#\210\266\307\335!\210\211\211\207" [vhdl-port-list vhdl-include-group-comments vhdl-actual-generic-name vhdl-include-port-comments vhdl-auto-align error "ERROR: No port read" message "Pasting port as constants..." vhdl-port-flatten indent-according-to-mode current-indentation nil (decl always) vhdl-paste-group-comment 4 vhdl-insert-keyword "CONSTANT " vhdl-replace-string " : " 2 " := " ";" 3 vhdl-comment-insert-inline t "\n" vhdl-align-region-groups 1 "Pasting port as constants...done"] 11 (#$ . 381135) nil])#@71 Paste ports as internal signals. (fn &optional INITIALIZE NO-INDENT) (defalias 'vhdl-port-paste-signals #[512 "\204�\306\307!\207\310\311!\210\211\204�\312 \210\313 \314\211\211\211\211\211\211\211\3158\211\203\246`\262 \211\203\232\211@\262 \316>\203>�\317\320 8 \"\210A@\203P�A@\321\261\210\202T�\322\323!\210@\262\203v�\324\n@\"c\210A\262\203Y�\325c\210\202Y�\3268\262A@\262\327\330 p\331\332#\216\333\f!\210\334\262\203\326�@@@\262\335\336\337Q #\203\316�\340 \331\341\"\216\324 \")\262\262\342\327\314 $\262\334\225\262\202\237�A\262\202\223�*\266\343\261\210 \203@\3158\203@\3158\226\344\232\203@\345\335\346\326 8\"\203\347\202=\335\350\326 8\"\203\347\202=\335\351\326 8\"\203 \347\202=\335\352\326 8\"\203.\353\202=\335\354\326 8\"\203<\355\202=\356\261\210\357c\210;\203O\3158\204[<\203\210\3608\203\210\361;\203u\315 8\203u\362\363\364\315\f8\365Q\"\202{;\205{\366<\205\204\360\n8P\327\"\210\211A\262\211\203'�\367c\210 j\210\202'�=\203\246\370 `\371#\210\266\n\310\372!\207" [vhdl-port-list vhdl-include-group-comments vhdl-actual-port-name case-fold-search vhdl-mode-ext-syntax-table vhdl-actual-generic-name error "ERROR: No port read" message "Pasting port as signals..." indent-according-to-mode current-indentation nil 2 (decl always) vhdl-paste-group-comment 5 " " vhdl-insert-keyword "SIGNAL " vhdl-replace-string ", " 3 t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table 0 string-match "\\<" "\\>" match-data #[0 "\301\300\302\"\207" [V0 set-match-data t] 3] replace-match " : " "IN" " := " "integer" "0" "natural" "positive" "real" "0.0" "(.+)" "(others => '0')" "'0'" ";" 4 vhdl-comment-insert-inline format "%-6s" "[" "] " " " "\n" vhdl-align-region-groups 1 "Pasting port as signals...done" vhdl-include-direction-comments vhdl-include-port-comments vhdl-auto-align] 19 (#$ . 382108) nil])#@66 Paste ports as signal initializations. (fn &optional NO-INDENT) (defalias 'vhdl-port-paste-initializations #[256 "\204�\303\304!\207\305\306!\210\307 \210\204�\310 \210\311 \312\211\211\3138\211\203\263�`\262\211\203\251�\211@\262\3138\226\314\232\203\216�@@\262\315 \"c\210\316\317\320\3218\"\203Q�\322\202\212�\317\323\3218\"\203_�\322\202\212�\317\324\3218\"\203m�\322\202\212�\317\325\3218\"\203{�\326\202\212�\317\327\3218\"\203\211�\330\202\212�\331\332\261\210\211A\262\211\203&�\313@8\226\314\232\203&�\333c\210j\210\202&�\n\203\263�\334`\335#\210\266\305\336!\210\211\211\207" [vhdl-port-list vhdl-actual-port-name vhdl-auto-align error "ERROR: No port read" message "Pasting port as initializations..." vhdl-port-flatten indent-according-to-mode current-indentation nil 2 "IN" vhdl-replace-string " <= " string-match "integer" 3 "0" "natural" "positive" "real" "0.0" "(.+)" "(others => '0')" "'0'" ";" "\n" vhdl-align-region-groups 1 "Pasting port as initializations...done"] 12 (#$ . 384100) nil])#@34 Paste as a bare-bones testbench. (defalias 'vhdl-port-paste-testbench #[0 "\204�\306\307!\207\310\311 @\"\312\211\211\211\211\211\211 \313=\204a�\311\f \310#\314\315\316 !Q\262\317!\203]�\320\321\322Q!\203J�\323!\210\324 \210\325\312!\210\202a� \326=\203V�\312\262\202a�\306\327!\210\202a�\323!\210 \326=\203k�\203\312� \203}�\330\331@\332Q!\210db\210\202\203�\333 \210\334c\210@\203\224�\335 \210\334c\210\333 \210\334c\210\336\337!\210c\210\336\340!\210A\341>\203\252�\342c\210\342c\210\336\343!\210\344\345!\204\273�\336\337!\210\346\261\210\334c\210\333 \210\342c\210BA\347\232\203\333�\350\351\312C#\202\341�\311B@\"\262\352\353  #\210 \326=\204\367�\342c\210\202Cp\262\311D \354\nQ\310#\314\315\316 !Q\262\317!\203 \320\321\322Q!\204 \306\327!\210\323!\210\324 \210\325\312!\210 \203=\330\355@\332Q!\210db\210\202C\333 \210\334c\210\336\356!\210c\210\336\357!\210c\210\336\340!\210\334c\210Ej\210\360 \204n\361\310!\210\334c\210Ej\210A@\203\206\362c\210Ej\210\363\310!\210\334c\210Ej\210\364c\210Ej\210\365F\310\"\210\342c\210G\347\232\204\255\342c\210`\262\366G!\210\367`\"\210`\262\334c\210\333 \210\342c\210H\203\311I \354\nQ\"\262\342c\210\336\370!\210c\210\336\357!\210c\210\336\371!\210Ej\210\336\372!\210\342\261\210Ej\210\336\373!\210\336\343!\210\374\261\210\333 \210\342c\210\211b\210\375\344\345!?\205\376\377\310$\210\201L�c\210Ej\210\201M�\311J@\"\310\"\210\342c\210K\347\232\204F\342c\210`\262\366K!\210\367`\"\210\342c\210Ej\210 \313=\204jp\262\203bq\210\201N� \210q\210\201N� \210\352\201O�\201P�\201Q�  #\205\207\201P�\201R� \"\205\225\201P�\201R� \"Q\")\207" [vhdl-port-list vhdl-testbench-entity-name case-fold-search vhdl-testbench-create-files vhdl-testbench-entity-file-name vhdl-testbench-include-header error "ERROR: No port read" t vhdl-replace-string nil none "." file-name-extension buffer-file-name file-exists-p y-or-n-p "File \"" "\" exists; overwrite? " find-file erase-buffer set-buffer-modified-p separate "ERROR: Pasting port as testbench...aborted" vhdl-template-header "Testbench for design \"" "\"" vhdl-comment-display-line "\n\n" vhdl-template-package-std-logic-1164 vhdl-insert-keyword "ENTITY " " IS" (unit all) "\n" "END " vhdl-standard-p 87 ";" "" read-from-minibuffer "architecture name: " message "Pasting port as testbench \"%s(%s)\"..." " " "Testbench architecture for design \"" "ARCHITECTURE " " OF " vhdl-use-direct-instantiation vhdl-port-paste-component "-- component generics\n" vhdl-port-paste-constants "-- component ports\n" vhdl-port-paste-signals vhdl-insert-string-or-file indent-region "CONFIGURATION " " IS\n" "FOR " "END FOR;\n" ";\n\n" vhdl-template-begin-end "ARCHITECTURE" 0 vhdl-testbench-include-library vhdl-insert-empty-lines vhdl-testbench-architecture-name vhdl-minibuffer-local-map vhdl-testbench-architecture-file-name vhdl-basic-offset vhdl-testbench-initialize-signals vhdl-testbench-declarations vhdl-testbench-include-configuration vhdl-testbench-configuration-name vhdl-testbench-dut-name vhdl-testbench-statements "-- component instantiation\n" vhdl-port-paste-instance save-buffer "%s" format "Pasting port as testbench \"%s(%s)\"...done" "\n File created: \"%s\""] 16 (#$ . 385145) nil])#@52 Variable to hold last subprogram interface parsed. (defvar vhdl-subprog-list nil (#$ . 388437))#@63 Indicates whether an subprogram interface has been flattened. (defvar vhdl-subprog-flattened nil (#$ . 388538))#@68 Flatten interface list so that only one parameter exists per line. (defalias 'vhdl-subprog-flatten #[0 "\204�\302\303!\207\304\305!\210\3068\307\211\211\211\203@�@\262@\262\211\2039�\211@CAB\262\310C\"\262\211A\262\202�A\262\202�@A@\3118\3128\3138\257\314\304\315!\207" [vhdl-subprog-list vhdl-subprog-flattened error "ERROR: No subprogram interface has been read" message "Flattening subprogram interface..." 2 nil append 3 4 5 t "Flattening subprogram interface...done"] 12 (#$ . 388655) nil])#@60 Get interface information from a subprogram specification. (defalias 'vhdl-subprog-copy #[0 "\212\304\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\305\306 p\307\310#\216\311 !\210\3122`\262\304\210\313\314!\2034�\315\225b\210\316\317\304\305#\203Q�\315\225b\203Q�\212\320u\210\321 \210`X)\204V�\322\312\323\"\210\324\325!\262\326\327!\203e�\330\202f�\331\262\326\332!?\262\333\334\"\210\335 \262\206\201�\336\337\305\"\262\204\336\340\305\"\205\222�\324\341!\262\f\336\342!\210\324\341!C\262 \336\343\305\"\203\262�\344 \324\341!C\"\262 \202\236�\336\345!\210\336\346\305\"\205\300�\324\341!\262\n\336\347!\210\324\341!\262 \304\262\313\350!\203\355�\351`\321 \210`\"\336\352\305\"\205\347�\324\341!Q\262 \202\316�\203\n\353\354\n\"\203\n\327\224\304O\262\315\341\224O\262 \353\355\n\"\210\315\341\225O\262 \304\262\336\356\305\"\203J\336\357!\210\324\341!\262\313\350!\203J\351`\321 \210`\"\336\357\305\"\205D\324\341!Q\262\202+\203j\353\354 \"\203j\327\224\304O\262\315\341\224O\262\360 \210\361\304w\210\204\336\362\305\"\205}\324\341!\262\360 \210\336\363\305\"\262\204\231\336\362\305\"\205\227\324\341!\262\335 \262\336\364!\210\326\365!\203\347\336\366!\210\324\341!\262\203\312\353\354\"\203\312\327\224\304O\262\315\341\224O\262\353\355\"\210\315\341\225O\262\204\347\336\362\305\"\205\345\324\341!\262\204\370\336\362\305\"\205\366\324\341!\262\344 \f     \257C\"\262 \335 \262\202\203�\333\367\"\210\3040*\262\266\2031\370!\266\220\202B\f\f\f\257\304\211\266\220)\207" [case-fold-search vhdl-mode-ext-syntax-table vhdl-subprog-list vhdl-subprog-flattened nil t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table parse looking-at "[ \n \f]*\\((\\|;\\|is\\>\\)" 0 re-search-backward "^\\s-*\\(\\(procedure\\)\\|\\(\\(pure\\|impure\\)\\s-+\\)?function\\)\\s-+\\(\"?\\w+\"?\\)[ \n \f]*\\(\\((\\)\\|;\\|is\\>\\)" -1 forward-sexp throw "ERROR: Not within a subprogram specification" match-string-no-properties 5 match-string 2 procedure function 7 message "Reading interface of subprogram \"%s\"..." vhdl-parse-group-comment vhdl-parse-string ")[ \n \f]*\\(;\\|\\(is\\|return\\)\\>\\)" "\\(constant\\|signal\\|variable\\|file\\|quantity\\|terminal\\)[ \n \f]*" 1 "\\(\\\\[^\\]+\\\\\\|\\w+\\)[ \n \f]*" ",[ \n \f]*\\(\\\\[^\\]+\\\\\\|\\w+\\)[ \n \f]*" append ":[ \n \f]*" "\\(in\\|out\\|inout\\|buffer\\|linkage\\)[ \n \f]+" "\\([^():;\n]+\\)" "(" buffer-substring-no-properties "\\([^():;\n]*\\)" string-match "\\(\\s-*--\\s-*\\)\\(.*\\)" "\\(\\(\\s-*\\S-+\\)+\\)\\s-*" ":=[ \n \f]*" "\\([^();\n]*\\)" vhdl-forward-syntactic-ws " " "--\\s-*\\([^\n]*\\)" ")\\s-*" "\\(;\\|\\(is\\|\\(return\\)\\)\\>\\)\\s-*" 3 "[ \n \f]*\\(.+\\)[ \n \f]*\\(;\\|is\\>\\)\\s-*" "Reading interface of subprogram \"%s\"...done" error] 27 (#$ . 389184) nil])#@49 Paste as a subprogram specification. (fn KIND) (defalias 'vhdl-subprog-paste-specification #[257 "\306 \210i\3078\310\211\211\211\311A@\312=\203�\313\202�\314!\210@c\210\2047�\315=\2030�\316c\210\202D\311\317!\210\202D`\262\320c\210 \204I�\321c\210\n\\j\210i\262\203\364�@\262 \322D>\203d�\323\3248\"\210\211A@\203q�\211A@\325\261\210\211@\262\203\213�@c\210A\262\203u�\326c\210\202u�\327c\210\3078\203\233�\3078\325\261\210\3308c\210\3318\203\255�\332\3318\261\210A\203\270�\316c\210\202\322�\333c\210\3308\204\322�\315=\203\316�\316c\210\202\322�\311\317!\210\f\203\343�\3348\203\343�\335\3348\336\"\210A\262\203L�\321c\210j\210\202L�\3308\2039\321c\210j\210 \322D>\203\323\3348\"\210\337\3308\261\210\315=\203$\316c\210\202(\311\317!\210\f\2039\3318\2039\335\3318\336\"\210 \203D\340`\341\336$\210\342=\205h\321c\210\343\344\345!?\205cA@\312=\203b\346\202c\347@#\207" [vhdl-subprog-list vhdl-argument-list-indent vhdl-basic-offset vhdl-include-group-comments vhdl-include-port-comments vhdl-auto-align indent-according-to-mode 2 nil vhdl-insert-keyword procedure "PROCEDURE " "FUNCTION " decl ";" " is" " (" "\n" always vhdl-paste-group-comment 6 " " ", " " : " 3 4 " := " ")" 5 vhdl-comment-insert-inline t "return " vhdl-align-region-groups 1 body vhdl-template-begin-end vhdl-standard-p 87 "PROCEDURE" "FUNCTION"] 12 (#$ . 392136)])#@36 Paste as a subprogram declaration. (defalias 'vhdl-subprog-paste-declaration #[0 "\204�\301\302!\207\303\304@\"\210\305\306!\210\303\307@\"\207" [vhdl-subprog-list error "ERROR: No subprogram interface read" message "Pasting interface as subprogram declaration \"%s\"..." vhdl-subprog-paste-specification decl "Pasting interface as subprogram declaration \"%s\"...done"] 3 (#$ . 393556) nil])#@29 Paste as a subprogram body. (defalias 'vhdl-subprog-paste-body #[0 "\204�\301\302!\207\303\304@\"\210\305\306!\210\303\307@\"\207" [vhdl-subprog-list error "ERROR: No subprogram interface read" message "Pasting interface as subprogram body \"%s\"..." vhdl-subprog-paste-specification body "Pasting interface as subprogram body \"%s\"...done"] 3 (#$ . 393959) nil])#@29 Paste as a subprogram call. (defalias 'vhdl-subprog-paste-call #[0 "\204�\306\307!\207\310\211\211\211\211\311 \210\3128\262\313 \210\314 \262\315\316@\"\210@c\210\2041�\317c\210\202\230�`\262\320c\210 \204C�\321c\210\n\\j\210i\262\203\216�@\262 \322=\203[�\323\3248\"\210@@\325\261\210A\262\203n�\326\202o�\327c\210\f\203\201�\3308\203\201�\331\3308!\210\203F�\321c\210j\210\202F� \203\230�\332`\333#\210\315\334@\"\210\211\207" [vhdl-subprog-list vhdl-argument-list-indent vhdl-basic-offset vhdl-include-group-comments vhdl-include-port-comments vhdl-auto-align error "ERROR: No subprogram interface read" nil vhdl-subprog-flatten 2 indent-according-to-mode current-indentation message "Pasting interface as subprogram call \"%s\"..." ";" " (" "\n" always vhdl-paste-group-comment 6 " => " "," ");" 5 vhdl-comment-insert-inline vhdl-align-region-groups 1 "Pasting interface as subprogram call \"%s\"...done"] 10 (#$ . 394334) nil]) (defvar vhdl-expand-upper-case nil)#@64 Try expanding abbreviations from `vhdl-abbrev-list'. (fn OLD) (defalias 'vhdl-try-expand-abbrev #[257 "\211\2042�\305\306 `\"\210\307\203-�@;\203 �\310\311 P@\"\203&�@B\262A\262\202\f�\211\237\266\202\n\203U�\n@;\203E�\312\n@ \313#\203U�\n@;\204N�\n@\nA\211\2046�\n\204b�\211\203`�\314 \210\307\207\315\f\203m�\n@\226\202o�\n@\313\"\210\nA\313\207" [vhdl-abbrev-list he-search-string he-expand-list he-tried-table vhdl-expand-upper-case he-init-string he-dabbrev-beg nil string-match "^" he-string-member t he-reset-string he-substitute-string] 7 (#$ . 395340)])#@132 Also looks at the word before `(' in order to better match parenthesized expressions (e.g. for index ranges of types and signals). (defalias 'vhdl-he-list-beg #[0 "\212\3001�\301\302!\210\303\304!0\210\202�\210`)\207" [(error) backward-up-list 1 skip-syntax-backward "w_"] 2 (#$ . 395923)]) (byte-code "\301\300!\203\n�\204�\302\303\304\"\210\302\305\306\307!\"\210\302\310\306\311!\"\207" [viper-mode boundp defalias he-list-beg vhdl-he-list-beg vhdl-expand-abbrev make-hippie-expand-function (try-expand-dabbrev try-expand-dabbrev-all-buffers vhdl-try-expand-abbrev) vhdl-expand-paren (try-expand-list try-expand-list-all-buffers)] 4)#@54 Return the line number of the line containing point. (defalias 'vhdl-current-line #[0 "\214~\210\300e\301 \"T)\207" [count-lines line-beginning-position] 3 (#$ . 396569)])#@41 Delete entire line. (fn &optional ARG) (defalias 'vhdl-line-kill-entire #[256 "\300 \210\301\206 �\302!\207" [beginning-of-line kill-line 1] 3 (#$ . 396746) "p"])#@40 Kill current line. (fn &optional ARG) (defalias 'vhdl-line-kill #[256 "\300!\207" [vhdl-line-kill-entire] 3 (#$ . 396916) "p"])#@40 Copy current line. (fn &optional ARG) (defalias 'vhdl-line-copy #[256 "\212\300 \206�\301y\210\302`\")\207" [line-beginning-position 1 copy-region-as-kill] 5 (#$ . 397051) "p"])#@19 Yank entire line. (defalias 'vhdl-line-yank #[0 "\300 \210\301 \207" [beginning-of-line yank] 1 (#$ . 397238) nil])#@49 Hippie-expand current line. (fn &optional ARG) (defalias 'vhdl-line-expand #[256 "\303\304!\210\305\306\307\310!+\207" [hippie-expand-try-functions-list case-replace case-fold-search require hippie-exp t nil (try-expand-line try-expand-line-all-buffers) hippie-expand] 4 (#$ . 397359) "P"])#@59 Interchange this line with next line. (fn &optional ARG) (defalias 'vhdl-line-transpose-next #[256 "\300y\210\301\206 �\300!\210\302y\207" [1 transpose-lines -1] 3 (#$ . 397660) "p"])#@63 Interchange this line with previous line. (fn &optional ARG) (defalias 'vhdl-line-transpose-previous #[256 "\300y\210\301\302\206\n�\302Z!\210\303y\207" [1 transpose-lines 0 -1] 4 (#$ . 397851) "p"])#@29 Open a new line and indent. (defalias 'vhdl-line-open #[0 "\300\210\301 \207" [0 newline-and-indent] 1 (#$ . 398058) nil])#@106 Join lines. That is, call `delete-indentation' with `fill-prefix' so that it works within comments too. (defalias 'vhdl-delete-indentation #[0 "\301\302 )\207" [fill-prefix "-- " delete-indentation] 1 (#$ . 398188) nil])#@45 Move forward to next line with same indent. (defalias 'vhdl-forward-same-indent #[0 "`\300 \301\302!\210m\204�\303\304!\204�\300 V\203�\301\302!\210\202�\300 U\203)�\305 \207\306\307!\210b\210\310\207" [current-indentation beginning-of-line 2 looking-at "^\\s-*\\(--.*\\)?$" back-to-indentation message "No following line with same indent found in this block" nil] 4 (#$ . 398416) nil])#@50 Move backward to previous line with same indent. (defalias 'vhdl-backward-same-indent #[0 "`\300 \301\302!\210o\204�\303\304!\204�\300 V\203�\301\302!\210\202�\300 U\203)�\305 \207\306\307!\210b\210\310\207" [current-indentation beginning-of-line 0 looking-at "^\\s-*\\(--.*\\)?$" back-to-indentation message "No preceding line with same indent found in this block" nil] 4 (#$ . 398815) nil])#@27 Get some file statistics. (defalias 'vhdl-statistics-buffer #[0 "\300\211\211\211\211\301ed\"\212eb\210\302\303\304\305#\203)�\306\307!\203\"�\307\225b\210\202 �T\262\202 �eb\210m\204A�\310\311!\204:�T\262\312\313!\210\202,�eb\210\302\314\304\305#\203o�`d=\204o�\306\307!\203_�\307\225b\210\202D�T\262`d=\204D�\304u\210\202D�eb\210\302\315\304\305#\203\216�\306\307!\203\207�\307\225b\210\202r�T\262\202r�eb\210\302\316\304\305#\203\255�\306\307!\203\246�\307\225b\210\202\221�T\262\202\221�)\317\320\321 &\210\304\207" [0 count-lines re-search-forward "\\(--.*\n\\|\"[^\"\n]*[\"\n]\\)\\|;" nil t match-string 1 looking-at "^\\s-*\\(--.*\\)?$" beginning-of-line 2 "^\\s-*$" "^\\s-*--.*" "--.*" message "\nFile statistics: \"%s\"\n-----------------------\n# statements : %5d\n# code lines : %5d\n# empty lines : %5d\n# comment lines : %5d\n# comments : %5d\n# total lines : %5d\n" buffer-file-name] 15 (#$ . 399220) nil])#@106 Like `re-search-forward', but does not match within literals. (fn REGEXP &optional BOUND NOERROR COUNT) (defalias 'vhdl-re-search-forward #[1025 "\300\212\301$\211\262\203�\302 \303\304\"\216\305 )\262\204�)\211\203%�\211b\210\207" [nil re-search-forward match-data make-closure #[0 "\301\300\302\"\207" [V0 set-match-data t] 3] vhdl-in-literal] 10 (#$ . 400185)])#@107 Like `re-search-backward', but does not match within literals. (fn REGEXP &optional BOUND NOERROR COUNT) (defalias 'vhdl-re-search-backward #[1025 "\300\212\301$\211\262\203�\302 \303\304\"\216\305 )\262\204�)\211\203%�\211b\210\207" [nil re-search-backward match-data make-closure #[0 "\301\300\302\"\207" [V0 set-match-data t] 3] vhdl-in-literal] 10 (#$ . 400566)])#@41 Set current project to NAME. (fn NAME) (defalias 'vhdl-set-project #[257 "\211\302\232\203�\303\304\305!\210\202'�\306 \"\203 �\211\304\307\"\210\202'�\310\311\312\"!\210\313 \207" [vhdl-project vhdl-project-alist "" nil message "Current VHDL project: None" assoc "Current VHDL project: \"%s\"" vhdl-warning format "Unknown VHDL project: \"%s\"" vhdl-speedbar-update-current-project] 5 (#$ . 400949) (byte-code "\302\303\304 \305\302$)C\207" [completion-ignore-case vhdl-project-alist t completing-read "Project name: " nil] 5)])#@44 Set current project as default on startup. (defalias 'vhdl-set-default-project #[0 "\301\300\"\210\302 \207" [vhdl-project customize-set-variable customize-save-customized] 3 (#$ . 401492) nil])#@90 Set current project to NAME or unset if NAME is current project. (fn NAME TOKEN INDENT) (defalias 'vhdl-toggle-project #[771 "\301\232\203 �\302\202\f�!\207" [vhdl-project vhdl-set-project ""] 6 (#$ . 401693)])#@58 Write project setup for current project. (fn FILE-NAME) (defalias 'vhdl-export-project #[257 "\303!\262p\304\305!!\204�\306\305!\307\"\210\310!\204 �\311\312\"\207\313\307\211#q\210\314 \210\315\316\317!\320\321\322 \323\324\325\326!\327 \330\331\332 \333\334\335\261\210\336\337\n \"p\"\210\340c\210\341 \210\342p!\210\211q\207" [vhdl-version vhdl-project vhdl-project-alist abbreviate-file-name file-exists-p file-name-directory make-directory t file-writable-p error "ERROR: File not writable: \"%s\"" find-file-noselect erase-buffer ";; -*- Emacs-Lisp -*-\n\n" ";;; " file-name-nondirectory " - project setup file for Emacs VHDL Mode " "\n\n" ";; Project : " "\n" ";; Saved : " format-time-string "%Y-%m-%d %T " user-login-name "\n\n\n" ";; project name\n" "(setq vhdl-project \"" "\")\n\n" ";; project setup\n" "(vhdl-aput 'vhdl-project-alist vhdl-project\n'" pp vhdl-aget ")\n" save-buffer kill-buffer] 21 (#$ . 401913) (byte-code "\301\302\303@B\304\305\306\307 \206�\310\311!#\312\313 Q\"!\314\315\316!\205!�\317\320\211%C\207" [vhdl-project-file-name vhdl-resolve-env-variable vhdl-replace-string "\\(.*\\) \\(.*\\)" subst-char-in-string 32 95 vhdl-project-p error "ERROR: No current project" " " user-login-name read-file-name "Write project file: " file-name-absolute-p "" nil] 8)])#@93 Read project setup and set current project. (fn FILE-NAME &optional AUTO NOT-MAKE-CURRENT) (defalias 'vhdl-import-project #[769 "\303!\205Y�\3041R�\305!\210\306 \"G\307U\204\"�\310\301\"\210\311\312!\210\203+�\211\2024�\313\306 \"8@@\314 \210\315 \210?\205N�\316\317\n\203L�\320\202M�\312$\2620\207\210\321\322\323\"!\207" [vhdl-project vhdl-project-alist vhdl-compiler file-exists-p (error) load-file vhdl-aget 10 vhdl-adelete error "" 4 vhdl-update-mode-menu vhdl-speedbar-refresh message "Current VHDL project: \"%s\"; compiler: \"%s\"%s" " (auto-loaded)" vhdl-warning format "ERROR: Invalid project setup file: \"%s\""] 9 (#$ . 403232) (byte-code "\301\302\303@B\304\305 P\"!\306\307\310!\205�\311\312\313\314!%C\207" [vhdl-project-file-name vhdl-resolve-env-variable vhdl-replace-string "\\(.*\\) \\(.*\\)" " " user-login-name read-file-name "Read project file: " file-name-absolute-p "" nil t file-name-directory] 8)])#@37 Duplicate setup of current project. (defalias 'vhdl-duplicate-project #[0 "\302\303!\304 \"\305BC\"\306 \207" [vhdl-project-alist vhdl-project read-from-minibuffer "New project name: " vhdl-aget append vhdl-update-mode-menu] 6 (#$ . 404184) nil])#@46 Automatically load project setup at startup. (defalias 'vhdl-autoload-project #[0 "\301\211\203*�\302\303\304\305\306@B\307\310 P\"!!\"\262\211\206!�G\262A\262\202�\205E�\311\312@!\313\314V?#\210\211S\262A\262\202*�\207" [vhdl-project-file-name nil append file-expand-wildcards vhdl-resolve-env-variable vhdl-replace-string "\\(.*\\) \\(.*\\)" "* " user-login-name vhdl-import-project expand-file-name t 0] 11 (#$ . 404441)]) (byte-code "\302\303\304\305#\210\306\303\304\307#\210\310>\203\"� \203�\304 \210\202\"�\311\312\305\304#\210\305\207" [vhdl-project-autoload noninteractive defalias vhdl-auto-load-project vhdl-autoload-project nil make-obsolete "27.1" startup vhdl-run-when-idle 0.1] 4)#@45 Regexp to match start of construct to hide. (defconst vhdl-hs-start-regexp "\\(^\\)\\s-*\\(\\(generic\\|port\\)[ \n \f]*(\\|component\\>\\|\\(\\w\\|\\s_\\)+[ \n \f]*:[ \n \f]*\\(\\(component\\|configuration\\|entity\\)[ \n \f]+\\)?\\(\\w\\|\\s_\\)+\\([ \n \f]*(\\(\\w\\|\\s_\\)+)\\)?[ \n \f]*\\(generic\\|port\\)[ \n \f]+map[ \n \f]*(\\|\\(function\\|procedure\\)\\>\\|\\(\\(\\w\\|\\s_\\)+[ \n \f]*:[ \n \f]*\\)?\\(process\\|block\\)\\>\\|configuration\\>\\)" (#$ . 405162))#@81 Find end of construct to hide (for hideshow). Only search forward. (fn COUNT) (defalias 'vhdl-hs-forward-sexp-func #[257 "`\302\303 p\304\305#\216\306 !\210\307 \210\310\311!\203%�\312\225b\210\313u\210\314 \202\326�\310\315!\2033�\316\317\320\302#\202\326�\310\321!\203a�\312\225b\210\313u\210\314 \210`\262\322 \210\310\323!\203\\�\312\225b\210\313u\210\314 \210`\262b\202\326�\310\324!\203\231�\312\225b\210\322 \210\310\325!\203w�\314 \210\316\326\320\302#\203\204�\327 \204w�\330\331!\205\326�\316\332\320\302#\210\333\334!\210\335 \202\326�\310\336!\203\267�\312\225b\210\316\337\320\302#\205\326�\331\224\205\326�\340!\210\202\243�\310\341!\203\305�\316\342\320\302#\202\326�\310\343!\203\324�\344\345!\210\335 \202\326�b)\266\202)\207" [case-fold-search vhdl-mode-ext-syntax-table t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table beginning-of-line looking-at "^\\s-*\\(generic\\|port\\)[ \n \f]*(" 0 -1 forward-sexp "^\\s-*component\\>" re-search-forward "^\\s-*end\\s-+component\\>" nil "^\\s-*\\w+\\s-*:[ \n \f]*\\(\\(component\\|configuration\\|entity\\)[ \n \f]+\\)?\\w+\\(\\s-*(\\w+)\\)?[ \n \f]*\\(generic\\|port\\)\\s-+map[ \n \f]*(" vhdl-forward-syntactic-ws "port\\s-+map[ \n \f]*(" "^\\s-*\\(function\\|procedure\\)\\s-+\\(\\w+\\|\".+\"\\)" "(" "\\(;\\)\\|\\(\\<is\\>\\)" vhdl-in-literal match-string 2 "^\\s-*\\<begin\\>" backward-word-strictly 1 vhdl-forward-sexp "^\\s-*\\w+\\s-*:\\s-*block\\>" "^\\s-*\\(\\(\\w+\\s-*:\\s-*block\\>\\)\\|\\(end\\s-+block\\>\\)\\)" vhdl-hs-forward-sexp-func "^\\s-*\\(\\w+\\s-*:\\s-*\\)?process\\>" "^\\s-*end\\s-+process\\>" "^\\s-*configuration\\>" forward-word-strictly 4] 8 (#$ . 405652)])#@24 Initialize `hideshow'. (defalias 'vhdl-hideshow-init #[0 "\205�\301\302!\207" [vhdl-hideshow-menu vhdl-hs-minor-mode 1] 2 (#$ . 407375)])#@69 Toggle hideshow minor mode and update menu bar. (fn &optional ARG) (defalias 'vhdl-hs-minor-mode #[256 "\303\304!\210\305\306!\204�\307\310!\207\311\236\204�\311 \312\313\314\312\257B\n\203-�\315\316\317\312\320$\210\2023�\321\316\317\320#\210\322!\210\323 \207" [hs-special-modes-alist vhdl-hs-start-regexp vhdl-hide-all-init require hideshow boundp hs-block-start-mdata-select vhdl-warning-when-idle "Install included `hideshow.el' patch first (see INSTALL file)" vhdl-mode nil "--\\( \\|$\\)" vhdl-hs-forward-sexp-func add-hook hs-minor-mode-hook hs-hide-all t remove-hook hs-minor-mode force-mode-line-update] 7 (#$ . 407520) "P"])#@56 Return point if within translate-off region, else nil. (defalias 'vhdl-within-translate-off #[0 "\212\300\301\302\303#)\205�\304\305!\306\232\205�`\207" [re-search-backward "^\\s-*--\\s-*pragma\\s-*translate_\\(on\\|off\\)\\s-*\n" nil t match-string 1 "off"] 4 (#$ . 408169)])#@81 Return point before translate-off pragma if before LIMIT, else nil. (fn LIMIT) (defalias 'vhdl-start-translate-off #[257 "\300\301\302#\205\n�\303\224\207" [re-search-forward "^\\s-*--\\s-*pragma\\s-*translate_off\\s-*\n" t 0] 5 (#$ . 408453)])#@79 Return point after translate-on pragma if before LIMIT, else nil. (fn LIMIT) (defalias 'vhdl-end-translate-off #[257 "\300\301\302#\207" [re-search-forward "^\\s-*--\\s-*pragma\\s-*translate_on\\s-*\n" t] 5 (#$ . 408705)])#@88 Match a translate-off block, setting match-data and returning t, else nil. (fn LIMIT) (defalias 'vhdl-match-translate-off #[257 "`W\205(�\301 \206�\302!\303\211\205%�\304!\206�\305D!\210\211b\262)\262\207" [case-fold-search vhdl-within-translate-off vhdl-start-translate-off t vhdl-end-translate-off set-match-data] 6 (#$ . 408935)])#@143 Match, and move over, any declaration item after point. Adapted from `font-lock-match-c-style-declaration-item-and-skip-to-next'. (fn LIMIT) (defalias 'vhdl-font-lock-match-item #[257 "\30010�\214e}\210\301\302!\205-�\303 \304\305\"\216\306\225b\210\301\307!\203&�\306\225b\202*�\310\210\311)\262)0\207\210\311\207" [(error) looking-at "\\s-*\\([a-zA-Z]\\w*\\)" match-data make-closure #[0 "\301\300\302\"\207" [V0 set-match-data t] 3] 1 "\\(\\s-*,\\)" nil t] 5 (#$ . 409287)])#@68 Mark single quotes as having string quote syntax in `c' instances. (defconst vhdl-font-lock-syntactic-keywords '(("\\('\\).\\('\\)" (1 (7 . 39)) (2 (7 . 39)))) (#$ . 409775))#@48 Regular expressions to highlight in VHDL Mode. (defvar vhdl-font-lock-keywords nil (#$ . 409955))#@129 For consideration as a value of `vhdl-font-lock-keywords'. This does highlighting of template prompts and directives (pragmas). (defvar vhdl-font-lock-keywords-0 nil (#$ . 410059))#@121 For consideration as a value of `vhdl-font-lock-keywords'. This does highlighting of keywords and standard identifiers. (defvar vhdl-font-lock-keywords-1 nil (#$ . 410246))#@122 For consideration as a value of `vhdl-font-lock-keywords'. This does context sensitive highlighting of names and labels. (defconst vhdl-font-lock-keywords-2 (byte-code "\300\301\302E\303\304\302E\305\306\307!\205�\310\311Q\312\302E\313\314\315E\316\317\320\321\322\257\323\306\307!\205(�\310\324Q\301\302E\325\326\302E\327\312\302E\330\331\332E\333\334D\335\336\337\340F\341\312\342E\343\301\344E\345\346D\347\350D\351\352D\353\312\354E\257\207" ["^\\s-*\\(architecture\\|configuration\\|context\\|entity\\|package\\(\\s-+body\\)?\\|\\(\\(impure\\|pure\\)\\s-+\\)?function\\|procedure\\|component\\)\\s-+\\(\\w+\\)" 5 font-lock-function-name-face "^\\s-*\\(architecture\\|configuration\\)\\s-+\\w+\\s-+of\\s-+\\(\\w+\\)" 2 "^\\s-*\\(\\w+\\)\\s-*:[ \n \f]*\\(\\(assert\\|block\\|case\\|exit\\|for\\|if\\|loop\\|next\\|null\\|postponed\\|process\\|" vhdl-standard-p ams "procedural\\|" "with\\|while\\)\\>\\|\\w+\\s-*\\(([^\n]*)\\|\\.\\w+\\)*\\s-*<=\\)" 1 "^\\s-*\\(\\w+\\)\\s-*:[ \n \f]*\\(\\w+\\)[ \n \f]*\\(--[^\n]*[ \n \f]+\\)*\\(generic\\|port\\)\\s-+map\\>" (1 font-lock-function-name-face) (2 font-lock-function-name-face) "^\\s-*\\(\\w+\\)\\s-*:[ \n \f]*\\(component\\|configuration\\|entity\\)\\s-+\\(\\w+\\)\\(\\.\\(\\w+\\)\\)?\\(\\s-*(\\(\\w+\\))\\)?" (1 font-lock-function-name-face) (3 font-lock-function-name-face) (5 font-lock-function-name-face nil t) (7 font-lock-function-name-face nil t) "^\\s-*end\\s-+\\(\\(architecture\\|block\\|case\\|component\\|configuration\\|context\\|entity\\|for\\|function\\|generate\\|if\\|loop\\|package\\(\\s-+body\\)?\\|procedure\\|\\(postponed\\s-+\\)?process\\|" "units\\)\\s-+\\)?\\(\\w*\\)" "^\\s-*\\(\\w+\\s-*:\\s-*\\)?\\(exit\\|next\\)\\s-+\\(\\w*\\)" 3 "^\\s-*attribute\\s-+\\w+\\s-+of\\s-+\\(\\w+\\(,\\s-*\\w+\\)*\\)\\s-*:" "^\\s-*for\\s-+\\(\\w+\\(,\\s-*\\w+\\)*\\)\\>\\s-*\\(:[ \n \f]*\\(\\w+\\)\\|[^i ]\\)" (1 font-lock-function-name-face) (4 font-lock-function-name-face nil t) "^\\s-*library\\>" (vhdl-font-lock-match-item nil nil (1 font-lock-function-name-face)) "\\<\\(context\\|use\\)\\s-+\\(\\(entity\\|configuration\\)\\s-+\\)?\\(\\w+\\)\\(\\.\\(\\w+\\)\\)?\\((\\(\\w+\\))\\)?" (4 font-lock-function-name-face) (6 font-lock-function-name-face nil t) (8 font-lock-function-name-face nil t) "^\\s-*attribute\\s-+\\(\\w+\\)" vhdl-font-lock-attribute-face "^\\s-*\\(\\(sub\\)?\\(nature\\|type\\)\\|end\\s-+\\(record\\|protected\\)\\)\\s-+\\(\\w+\\)" font-lock-type-face "\\(:[^=]\\)" (vhdl-font-lock-match-item (progn (goto-char (match-beginning 1)) (skip-syntax-backward " ") (skip-syntax-backward "w_") (skip-syntax-backward " ") (while (= (preceding-char) 44) (backward-char 1) (skip-syntax-backward " ") (skip-syntax-backward "w_") (skip-syntax-backward " "))) (goto-char (match-end 1)) (1 font-lock-variable-name-face)) "\\(=>\\)" (vhdl-font-lock-match-item (progn (goto-char (match-beginning 1)) (skip-syntax-backward " ") (while (= (preceding-char) 41) (backward-sexp)) (skip-syntax-backward "w_") (skip-syntax-backward " ") (when (memq (preceding-char) '(110 78 124)) (goto-char (point-max)))) (goto-char (match-end 1)) (1 font-lock-variable-name-face)) "\\<\\(alias\\|for\\|group\\|quantity\\)\\s-+\\w+\\s-+\\(across\\|in\\|is\\)\\>" (vhdl-font-lock-match-item (progn (goto-char (match-end 1)) (match-beginning 2)) nil (1 font-lock-variable-name-face)) "^\\s-*\\(`\\w+\\)" font-lock-preprocessor-face] 19) (#$ . 410425))#@113 For consideration as a value of `vhdl-font-lock-keywords'. This does highlighting of words with special syntax. (defvar vhdl-font-lock-keywords-3 nil (#$ . 413835))#@113 For consideration as a value of `vhdl-font-lock-keywords'. This does highlighting of additional reserved words. (defvar vhdl-font-lock-keywords-4 nil (#$ . 414006))#@120 For consideration as a value of `vhdl-font-lock-keywords'. This does background highlighting of translate-off regions. (defconst vhdl-font-lock-keywords-5 '((vhdl-match-translate-off (0 vhdl-font-lock-translate-off-face append))) (#$ . 414177))#@31 Face name to use for prompts. (defvar vhdl-font-lock-prompt-face 'vhdl-font-lock-prompt-face (#$ . 414427))#@47 Face name to use for standardized attributes. (defvar vhdl-font-lock-attribute-face 'vhdl-font-lock-attribute-face (#$ . 414540))#@55 Face name to use for standardized enumeration values. (defvar vhdl-font-lock-enumvalue-face 'vhdl-font-lock-enumvalue-face (#$ . 414675))#@59 Face name to use for standardized functions and packages. (defvar vhdl-font-lock-function-face 'vhdl-font-lock-function-face (#$ . 414818))#@34 Face name to use for directives. (defvar vhdl-font-lock-directive-face 'vhdl-font-lock-directive-face (#$ . 414963))#@49 Face name to use for additional reserved words. (defvar vhdl-font-lock-reserved-words-face 'vhdl-font-lock-reserved-words-face (#$ . 415085))#@45 Face name to use for translate-off regions. (defvar vhdl-font-lock-translate-off-face 'vhdl-font-lock-translate-off-face (#$ . 415232)) (byte-code "\301\203&�\302\303@@\304#\262\305\306\307D\310@@\311QF!\210A\262\202�\266\312\313\301\314\315\316%\210\317\313\320\321#\210\317\313\322\321#\210\317\313\323\321#\210\317\313\324\321#\210\317\313\325\321#\210\317\313\326\321#\207" [vhdl-special-syntax-alist nil vhdl-function-name "vhdl-font-lock" "face" eval defvar quote "Face name to use for " "." custom-declare-group vhdl-highlight-faces "Faces for highlighting." :group vhdl-highlight custom-add-to-group font-lock-comment-face custom-face font-lock-string-face font-lock-keyword-face font-lock-type-face font-lock-function-name-face font-lock-variable-name-face] 9) (custom-declare-face 'vhdl-font-lock-prompt-face '((((min-colors 88) (class color) (background light)) (:foreground "Red1" :bold t)) (((class color) (background light)) (:foreground "Red" :bold t)) (((class color) (background dark)) (:foreground "Pink" :bold t)) (t (:inverse-video t))) "Font lock mode face used to highlight prompts." :group 'vhdl-highlight-faces) (custom-declare-face 'vhdl-font-lock-attribute-face '((((class color) (background light)) (:foreground "Orchid")) (((class color) (background dark)) (:foreground "LightSteelBlue")) (t (:italic t :bold t))) "Font lock mode face used to highlight standardized attributes." :group 'vhdl-highlight-faces) (custom-declare-face 'vhdl-font-lock-enumvalue-face '((((class color) (background light)) (:foreground "SaddleBrown")) (((class color) (background dark)) (:foreground "BurlyWood")) (t (:italic t :bold t))) "Font lock mode face used to highlight standardized enumeration values." :group 'vhdl-highlight-faces) (custom-declare-face 'vhdl-font-lock-function-face '((((class color) (background light)) (:foreground "Cyan4")) (((class color) (background dark)) (:foreground "Orchid1")) (t (:italic t :bold t))) "Font lock mode face used to highlight standardized functions and packages." :group 'vhdl-highlight-faces) (custom-declare-face 'vhdl-font-lock-directive-face '((((class color) (background light)) (:foreground "CadetBlue")) (((class color) (background dark)) (:foreground "Aquamarine")) (t (:italic t :bold t))) "Font lock mode face used to highlight directives." :group 'vhdl-highlight-faces) (custom-declare-face 'vhdl-font-lock-reserved-words-face '((((class color) (background light)) (:foreground "Orange" :bold t)) (((min-colors 88) (class color) (background dark)) (:foreground "Yellow1" :bold t)) (((class color) (background dark)) (:foreground "Yellow" :bold t)) (t nil)) "Font lock mode face used to highlight additional reserved words." :group 'vhdl-highlight-faces) (custom-declare-face 'vhdl-font-lock-translate-off-face '((((class color) (background light)) (:background "LightGray")) (((class color) (background dark)) (:background "DimGray")) (t nil)) "Font lock mode face used to background highlight translate-off regions." :group 'vhdl-highlight-faces) (byte-code "\211\2039�\301\302\303\304@@\305#\306\307\310\311@8DD\312\310\313@8DD\314BBD\315@@\316Q\317BBBB!\210\211A\262\202�\207" [vhdl-special-syntax-alist eval defface vhdl-function-name "vhdl-font-lock" "face" quote ((class color) (background light)) :foreground 2 ((class color) (background dark)) 3 ((t nil)) "Font lock mode face used to highlight " "." (:group 'vhdl-highlight-faces)] 10)#@27 Initialize fontification. (defalias 'vhdl-font-lock-init #[0 "\306\307Q\310\311\312F\313\314 \312\"\315Q\310\316\312F\317\320\321EE\322 P\323\324E\f\323\325E \323\326E#\323\326E$\323\327E%\323\330E&\323\331E\257'(\332\203e�\333@A@\334Q\323\335\336@@\337#\340@8FB\262A\262\202B�\262)*\323\341EC+\342\n,\205z�'-\204\204�.\205\206�+/\205\215�)0\205\224�12\205\233�3&\2114\207" [vhdl-template-prompt-syntax vhdl-directive-keywords vhdl-font-lock-keywords-0 vhdl-attributes-regexp vhdl-types-regexp vhdl-functions-regexp "\\(^\\|[ (.']\\)\\(<" ">\\)" 2 vhdl-font-lock-prompt-face t "--\\s-*\\<" regexp-opt "\\>\\s-+\\(.*\\)$" vhdl-font-lock-directive-face "^#[ ]*\\(\\w+\\)\\([ ]+\\(\\w+\\)\\)?" (1 font-lock-builtin-face) (3 font-lock-variable-name-face nil t) "'" 1 vhdl-font-lock-attribute-face font-lock-type-face vhdl-font-lock-function-face vhdl-font-lock-enumvalue-face font-lock-constant-face font-lock-keyword-face nil "\\(" "\\)" vhdl-function-name "vhdl-font-lock" "face" 4 vhdl-font-lock-reserved-words-face append vhdl-packages-regexp vhdl-enum-values-regexp vhdl-constants-regexp vhdl-keywords-regexp vhdl-font-lock-keywords-1 vhdl-special-syntax-alist vhdl-font-lock-keywords-3 vhdl-reserved-words-regexp vhdl-font-lock-keywords-4 vhdl-highlight-keywords vhdl-highlight-forbidden-words vhdl-highlight-verilog-keywords vhdl-highlight-special-words vhdl-highlight-names vhdl-font-lock-keywords-2 vhdl-highlight-translate-off vhdl-font-lock-keywords-5 vhdl-font-lock-keywords] 9 (#$ . 418670)]) (vhdl-font-lock-init)#@49 Re-initialize fontification and fontify buffer. (defalias 'vhdl-fontify-buffer #[0 "\302\303?\304BBB\305\306!\203�\306 \210\307 \210\310\303!\210\310\311!\207" [vhdl-highlight-case-sensitive font-lock-defaults vhdl-font-lock-keywords nil (((95 . "w")) beginning-of-line) fboundp font-lock-unset-defaults font-lock-set-defaults font-lock-mode t] 4 (#$ . 420236) nil])#@67 Initialize custom face and page settings for PostScript printing. (defalias 'vhdl-ps-print-settings #[0 "\203� \204�\306\302!\210\307\306\303!\210\310\306\304!\210\311\312\205h�\306\313!\210\312 \306\314!\210\315\f\306\316!\210\317\306\320!\210\321\306\322!\210\323\306\324!\210\325\326=\205h�\306\327!\210\330\306\331!\210\330\306\332!\210\330\211\207" [vhdl-print-customize-faces ps-print-color-p ps-bold-faces ps-italic-faces ps-underlined-faces ps-always-build-face-reference make-local-variable (font-lock-keyword-face font-lock-type-face vhdl-font-lock-attribute-face vhdl-font-lock-enumvalue-face vhdl-font-lock-directive-face) (font-lock-comment-face font-lock-function-name-face font-lock-type-face vhdl-font-lock-attribute-face vhdl-font-lock-enumvalue-face vhdl-font-lock-directive-face) (font-lock-string-face) t ps-landscape-mode ps-number-of-columns 2 ps-font-size 7.0 ps-header-title-font-size 10.0 ps-header-font-size 9.0 ps-header-offset 12.0 letter ps-inter-column 40.0 ps-left-margin ps-right-margin vhdl-print-two-column ps-paper-type] 2 (#$ . 420611)])#@33 Initialize PostScript printing. (defalias 'vhdl-ps-print-init #[0 "\300\301\302\303\304$\207" [add-hook ps-print-hook vhdl-ps-print-settings nil t] 5 (#$ . 421717)])#@81 Cache with entities and corresponding architectures for each project/directory. (defvar vhdl-entity-alist nil (#$ . 421888))#@55 Cache with configurations for each project/directory. (defvar vhdl-config-alist nil (#$ . 422018))#@49 Cache with packages for each project/directory. (defvar vhdl-package-alist nil (#$ . 422122))#@62 Cache with instantiated entities for each project/directory. (defvar vhdl-ent-inst-alist nil (#$ . 422221))#@66 Cache with design units in each file for each project/directory. (defvar vhdl-file-alist nil (#$ . 422334))#@49 Cache with source directories for each project. (defvar vhdl-directory-alist nil (#$ . 422447))#@99 Alist of design units simultaneously open in the current speedbar for each directory and project. (defvar vhdl-speedbar-shown-unit-alist nil (#$ . 422548))#@63 List of projects simultaneously open in the current speedbar. (defvar vhdl-speedbar-shown-project-list nil (#$ . 422709))#@54 List of projects and directories with updated files. (defvar vhdl-updated-project-list nil (#$ . 422836))#@64 List of modified files to be rescanned for hierarchy updating. (defvar vhdl-modified-file-list nil (#$ . 422947))#@46 Depth of instantiation hierarchy to display. (defvar vhdl-speedbar-hierarchy-depth 0 (#$ . 423066))#@90 Non-nil means project hierarchy is displayed in speedbar, directory hierarchy otherwise. (defvar vhdl-speedbar-show-projects nil (#$ . 423171))#@41 Return position of end of current unit. (defalias 'vhdl-get-end-of-unit #[0 "`\212\300\301\302\303#\203�\212\304\224b\210\305 \210h\306U?\205�o?)\204�\307\310\303#\210`)\207" [re-search-forward "^[ ]*\\(architecture\\|configuration\\|context\\|entity\\|package\\)\\>" nil 1 0 vhdl-backward-syntactic-ws 59 re-search-backward "^[ ]*end\\>"] 5 (#$ . 423320)])#@80 Like `match-string-no-properties' with down-casing. (fn NUM &optional STRING) (defalias 'vhdl-match-string-downcase #[513 "\300\"\211\205\n�\211\227\207" [match-string-no-properties] 5 (#$ . 423689)])#@54 Scan the context clause that precedes a design unit. (defalias 'vhdl-scan-context-clause #[0 "\300\212\301\302\300\303#\203/�\301\304\300\303#\203/�\305\306!\226\307\232\203/�\310\311!\203\n�\312\306!\313\314!BB\262\202\n�)\207" [nil re-search-backward "^[ ]*\\(architecture\\|configuration\\|context\\|entity\\|package\\)\\>" t "^[ ]*\\(end\\|use\\)\\>" match-string 1 "USE" looking-at "^[ ]*use[ \n \f]*\\(\\w+\\)\\.\\(\\w+\\)\\.\\w+" match-string-no-properties vhdl-match-string-downcase 2] 5 (#$ . 423898)])#@121 Scan contents of VHDL files in directory or file pattern NAME. (fn NAME &optional PROJECT UPDATE NUM-STRING NON-FINAL) (defalias 'vhdl-scan-directory-contents #[1281 "\306\307\"\210\310\311\"\310\312\"\211G\313U\203�C\2020�\211\203)�\314\315\"\2020�\316\315\317!#\2066�\320\321 \"8\206A�\322 @ A@@ A@A@\323\211\323\211C\323\211\323\211\211\211C\204f�\203\214�\321+\f\"\321,\f\"\321-\f\"\321. \"@\240\210\321/\f\"\f\204\234� \204\234�\324\325\"\210 \262 \203` G\262\324\326\203\265�\327\202\266�\330\206\274�\322$\210 \322\232\204\361�\323\2115 \203\352�\306\f@\"\204\342� @B\262 A\262\202\314�\211\237)\262\266 \203`6\204\324\331\203\327\202\330\206 \322\332\333 GZ_ \"%\210\334\f@!\323C\323C\323C\323C\323C\323C\323C\323C\335 \323\336\337   !#&#\266\n A\262\f\202\361�\204i\204s\203R\204R\n\262\203\243\312@8\204\234\340@8@\262\341\342A@@A@\3128\320 8%\210A\262\202v \262\203\321\n\340@8\"\211\262\203\344\321\3208\343@8\"\204\373@\262\341\344A@\3408\3438\312 8\320\n8&\210\202\373@\262\341\345A@\3408\3128\320 8%\210A\262\202\246\f\262\203*\312@8\204#@\262\341\346A@\3478\3508$\210A\262\202\351\n!\351 !\351\f!\206=\2117\235\203K7\266\202R\2117B7\210\204u\352\353\f\"\210\352\354\f\"\210\352\355\f\"\210\352\356\f\"\210\352\357\f\"\210\360\353\f\n#\210\360\354\f #\210\360\355\f\f#\210\360\356\f\242C#\210\360\357\f #\210\324\361\203\246\327\202\247\330\206\255\322$\210\204\272\324\362!\210\211\242\203\303\341\363!\210\203\315\204\3346\203\3348\203\334\364 !\210,\315\207" [vhdl-project-alist vhdl-speedbar-scan-limit ent-alist conf-alist pack-alist file-alist string-match "\\(.*[/\\]\\)\\(.*\\)" match-string 1 2 0 vhdl-get-source-files t vhdl-directory-files wildcard-to-regexp 3 vhdl-aget #1="" nil message "No such file: \"%s\"" "Scanning %s %s\"%s\"..." "directory" "files" "Scanning %s %s\"%s\"... (%2d%%)" floor 100.0 abbreviate-file-name vhdl--visit-file make-closure #[0 "\316@\317 p\320\321#\216\322A!\210\212\315\203)�\315\323 W\203)�\324\325\310\"\210\311\316\240\210\202\370eb\210\326\327\330\316#\203{�\331\332!\211\227\333\"\"\334 A@\203Z�\335\336A@\3378\310\340 &\266\202,�\307\307\242B\240\210\341\342\310\340 \3438\344 8\257#\266\202,�eb\210\326\345\330\316#\203�\331\332!\211\227\331\337!\211\227\333\"\"\3438'\333'\"\334 \203\273�\335\346A@\3378\310\340 &\210\202\372�\306\306\242B\240\210\305\305\242B\240\210\341\347 \310\340 \330\257#\210\341\342@\206\344�A@\3378\350'!\f\351 8\257#\210)\266\202~�eb\210\326\352\330\316#\203\326\331\332!\211\227B\3338B\"C\331\337!\211\227\334 \340 \353 \330\211\211\211\211\211\211\211\354\355!\2038\356\332!\262C\203T\335\357CA@\337C8\310&\210\202\320\304B\304\242B\240\210\326\360\n\316#\203\273\356\343!\262\361\356\332!\362\"\262\363 \210\364\365!\203\\\356\343!\262\366\337!\205\211\356\344!\262\366\337!\205\224\356\367!\262\366\337!?\205\240\356\344!\262\203\\@\257B\262A\262\202\242\341\370B\310\257#\210*\266\202eb\210\326\371\330\316#\203\370\331\337!\211\227\331\332!\333D\"\340 \353 \330\211\211\211\211\203\3678\202A@\203B\335\372\n\203\373\202\374 \f\203$\367\f8\202( A@ \2034\375 8\2028\337 8\310\340 &\266\f\202\331\334 \262\326\376\316#\203~\366\332!\226\377\232\203k\331\337!\262\227\310\340 FB\262\202F\331\337!\262\227\310\340 FB\262\202F\237\262\237\262\203\226\302\n\302\242B\240\210\202\236\303\n\303\242B\240\210\341\201D�  \203\321\n@\206\261  A@\337 8\3438\3448\3518\310\f\f\257\n\202\362 \310 \3678\3758\201E�8\201F�8\257\n#\266\f\202\331\314\203\314\323 W\203\324\201G�\310\"\210\311\316\240\210\202eb\210\326\345\330\316#\203\331\337!\211\227\331\332!\211\227\333\"\"\3438'\333'\"`\353 \201H�\330\211\326\201I�\316#\203�\313\203i\366\201J�!\204[\366\201K�!\203_\202dT\211\262\313X\203�\366\201J�!\203{\331\332!B\262\202=\366\201K�!\203\212\211A\262\202=\331\332!\211\227\331\343!\206\230\331\367!\366\201E�!\203\250\356\201L�!\206\256\211\205\256\211\227\356\201M�!\366\201E�!?\205\301\356\201L�!\356\201N�!\332\225b\210\301\301\242B\240\210\300\300\242B\240\210\201O�  \310\340 \n\n\n\n\n\201P�!\257\nC\"\262 \266\202=b\210\326\201Q�\316#\203\260\331\343!\366\367!\205\356\201F�!\356\201L�!\366\367!?\205,\356\201F�!\356\201E�!\361\356\332!\362\"\330\203\253@\201R�\232\204O@@\235\203\244\344@8\206W\374\227\227\232\203\244@\262\300\206l\3518\201S�\3518\300\242\"B\240\210\211@A@\3378\3438\3448 \206\217\3518 \206\230\3678  \257 \262\240\210A\262\202:\266\202\341\347 @ A@\337 8\344 8\257#\210\341\342  @\nA@\337\f8\350'!\3448\3518\257#\210\313\203\375\313V\203\375\324\201T�\310\"\210\311\316\240\210b)\266\f\202\341\201U�\310\307\242\306\242\305\242\304\242\303\242\302\242\301\242\300\242\257#\210\312\201O�\300\242\312\242\"\240*\266\202)\207" [V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table buffer-size message "WARNING: Scan limit (design units: file size) reached in file:\n \"%s\"" re-search-forward "^[ ]*entity[ \n \f]+\\(\\w+\\)[ \n \f]+is\\>" nil match-string-no-properties 1 vhdl-aget vhdl-scan-context-clause vhdl-warning-when-idle "Entity declared twice (used 1.): \"%s\"\n 1. in \"%s\" (line %d)\n 2. in \"%s\" (line %d)" 2 vhdl-current-line vhdl-aput ent-alist 3 4 "^[ ]*architecture[ \n \f]+\\(\\w+\\)[ \n \f]+of[ \n \f]+\\(\\w+\\)[ \n \f]+is\\>" "Architecture declared twice (used 1.): \"%s\" of \"%s\"\n 1. in \"%s\" (line %d)\n 2. in \"%s\" (line %d)" arch-alist vhdl-sort-alist 5 "^[ ]*configuration[ \n \f]+\\(\\w+\\)[ \n \f]+of[ \n \f]+\\(\\w+\\)[ \n \f]+is\\>" vhdl-get-end-of-unit vhdl-re-search-forward "\\<for[ \n \f]+\\(\\w+\\)" vhdl-match-string-downcase "Configuration declared twice (used 1.): \"%s\" of \"%s\"\n 1. in \"%s\" (line %d)\n 2. in \"%s\" (line %d)" "^[ ]*for[ \n \f]+\\(\\w+\\([ \n \f]*,[ \n \f]*\\w+\\)*\\)[ \n \f]*:[ \n \f]*\\(\\w+\\)[ \n \f]+" split-string "[ \n \f]*,[ \n \f]*" vhdl-forward-syntactic-ws looking-at "use[ \n \f]+\\(\\(entity\\)\\|configuration\\)[ \n \f]+\\(\\w+\\)\\.\\(\\w+\\)[ \n \f]*\\((\\(\\w+\\))\\)?" match-string 6 conf-alist "^[ ]*package[ \n \f]+\\(body[ \n \f]+\\)?\\(\\w+\\)[ \n \f]+is\\>" "Package%s declared twice (used 1.): \"%s\"\n 1. in \"%s\" (line %d)\n 2. in \"%s\" (line %d)" " body" #1# 7 "^[ ]*\\(component\\|function\\|procedure\\)[ \n \f]+\\(\\w+\\|\".*\"\\)" "COMPONENT" case-fold-search vhdl-mode-ext-syntax-table conf-key conf-entry pack-alist 8 9 "WARNING: Scan limit (hierarchy: file size) reached in file:\n \"%s\"" 0 "^[ ]*\\(\\w+\\)[ \n \f]*:[ \n \f]*\\(\\(\\w+\\)[ \n \f]+\\(--[^\n]*\n[ \n \f]*\\)*\\(generic\\|port\\)[ \n \f]+map\\>\\|component[ \n \f]+\\(\\w+\\)\\|\\(\\(entity\\)\\|configuration\\)[ \n \f]+\\(\\(\\w+\\)\\.\\)?\\(\\w+\\)\\([ \n \f]*(\\(\\w+\\))\\)?\\|\\(\\(for\\|if\\)\\>[^;:]+\\<generate\\>\\|block\\>\\)\\)\\|\\(^[ ]*end[ \n \f]+\\(generate\\|block\\)\\>\\)" 14 16 11 13 10 append reverse "^[ ]*for[ \n \f]+\\(\\w+\\([ \n \f]*,[ \n \f]*\\w+\\)*\\)[ \n \f]*:[ \n \f]*\\(\\w+\\)[ \n \f]+\\(--[^\n]*\n[ \n \f]*\\)*use[ \n \f]+\\(\\(entity\\)\\|configuration\\)[ \n \f]+\\(\\(\\w+\\)\\.\\)?\\(\\w+\\)\\([ \n \f]*(\\(\\w+\\))\\)?" "all" vhdl-delete "WARNING: Scan limit (hierarchy: instances per architecture) reached in file:\n \"%s\"" file-alist] 33] 4 vhdl-warning-when-idle "Architecture of non-existing entity: \"%s\" of \"%s\"\n in \"%s\" (line %d)" 5 "Configuration of non-existing architecture: \"%s\" of \"%s(%s)\"\n in \"%s\" (line %d)" "Configuration of non-existing entity: \"%s\" of \"%s\"\n in \"%s\" (line %d)" "Package body of non-existing package: \"%s\"\n in \"%s\" (line %d)" 7 8 vhdl-sort-alist vhdl-adelete vhdl-entity-alist vhdl-config-alist vhdl-package-alist vhdl-ent-inst-alist vhdl-file-alist vhdl-aput "Scanning %s %s\"%s\"...done" "Scanning directory...done" "Scanning is incomplete.\n --> see user option `vhdl-speedbar-scan-limit'" vhdl-save-cache case-fold-search noninteractive vhdl-updated-project-list vhdl-speedbar-save-cache] 49 (#$ . 424422)])#@98 Scan the contents of all VHDL files found in the directories and files of PROJECT. (fn PROJECT) (defalias 'vhdl-scan-project-contents #[257 "\302\303\"8\206\n�\304\305\303\"A@!\306\303\"8\206�\307\310\211\211\211\211\211\311\312 \"\210\311\313 \"\210\311\314 \"\210\311\315 \"\210\311\316 \"\210\317\320!\210\203\200�\305 @!\262\321\322\"\210\323\324\"\262\323\306\"\262\211\325!\203o�\307\202q�QB\262A\262 \202D�\326!\262\203\266�@\262\321\327\"\203\246�\330 \331\323\324 \"!\"\262 \202\257�\330 C\"\262 A\262\202\206�\307\232\204\343�\310\203\336�\321\n@\"\204\326�@B\262A\262 \202\277�\237)\262 \317\332!\210\310\262G\262\324\262\2034\333\334\n@!!\262\335 \310\336\337 # A%\210\340!\211\235\203 \202$\211B\262\262A\262 T\262\202\362�\341\342 \237C#\210\317\343 \"\207" [vhdl-project-alist case-fold-search 2 vhdl-aget (#1="") vhdl-resolve-env-variable 3 #1# nil vhdl-adelete vhdl-entity-alist vhdl-config-alist vhdl-package-alist vhdl-ent-inst-alist vhdl-file-alist message "Collecting source files..." string-match "\\(\\(-r \\)?\\)\\(.*\\)" match-string 1 file-name-absolute-p vhdl-resolve-paths "-r \\(.*[/\\]\\)" append vhdl-get-subdirs "Collecting source files...done" abbreviate-file-name expand-file-name vhdl-scan-directory-contents format "(%s/%s) " file-name-directory vhdl-aput vhdl-directory-alist "Scanning project \"%s\"...done"] 18 (#$ . 432991)])#@77 Update hierarchy information by contents of current buffer. (fn FILE-NAME) (defalias 'vhdl-update-file-contents #[257 "\306!\262\307!\310\2037@A@\235\2030@@\311 \312\n\206$�\"\312\f\206-�\"\312\2067�\"\312\206B�\"@\312\206M�\"\312\"\211@A@\3138\3148\3158\3168\3178 \206s�\f\310\211\310\211\n\203\270�\n@\262\312 \"\262A@\232\203\260�\3148\203\253�\320\303@\310\211\3148\310\257#\210\202\260�\321\303\"\210\nA\262 \202y� \203 @\262@\262\312 \"\262\3148\312\"A@\232\203\321\322\"\210\211A@\204\357�\203\f\320\303@A@\3138\3158\316 8\257#\210\202\321\303\"\210 A\262\nA\262 \202\270�\203A@\262\312 \"A@\232\2039\321\305\"\210A\262\202\203\217@\262\312\"\262A@\232\203\207\3238\203\202\320\324@\310\211\211\211\211\323\n8\317 8\325\f8\326 8\257\n#\210\202\207\321\324\"\210A\262\202A\203\334@\262\312\"\262\3238\232\203\325\211A@\203\320\320\324@A@\3138\3148\3158\316 8\310\211\211\211\257\n#\210\202\325\321\324\"\210A\262\202\217\203\357\327@\"\262 A\262\202\334\330\302 #\210\330\304 #\210\330\331#\210\330\332C#\210\333\334#\210 \203 \204& \204+ \204+\335!\210.\266\334A\262\202\n�\207" [vhdl-directory-alist vhdl-project vhdl-entity-alist ent-alist vhdl-config-alist conf-alist abbreviate-file-name file-name-directory nil vhdl-project-p vhdl-aget 2 3 4 5 7 vhdl-aput vhdl-adelete arch-alist 6 pack-alist 8 9 vhdl-delete vhdl-aput-delete-if-nil vhdl-package-alist vhdl-ent-inst-alist vhdl-scan-directory-contents t vhdl-speedbar-refresh vhdl-file-alist file-alist vhdl-speedbar-show-projects] 33 (#$ . 434462)])#@57 Update directory and hierarchy information in speedbar. (defalias 'vhdl-update-hierarchy #[0 "\302!\303 \205-�\205-�\203!�\304@!\206�\211\262A\262\202\f�\303\305 \210\211\205-�\306\307!\207" [vhdl-modified-file-list vhdl-speedbar-update-on-saving reverse nil vhdl-update-file-contents vhdl-speedbar-update-current-unit message "Updating hierarchy...done"] 4 (#$ . 436194)])#@208 Get instantiation hierarchy beginning in architecture ARCH-KEY of entity ENT-KEY. (fn ENT-ALIST-ARG CONF-ALIST-ARG ENT-KEY ARCH-KEY CONF-KEY-ARG CONF-INST-ALIST LEVEL INDENT &optional INCLUDE-TOP ENT-HIER) (defalias 'vhdl-get-hierarchy #[2568 " \303 \"\203�\303\3048 \"\202#�\305\3048!@A\3048\306\211\211\211\211\211\211\211\211\211\211\211\211\211\307U\203?�\310\311!\210\203I�T\262\235\203W�\312\313\"\210\203\245@\262 @\262\3148\262\3158\262\262\203\236�@@\316D\235\203\226�@A@\206\221�\317\227\232\204\236�A\262\202v�\314@8\206\247�\262\303 \"\262 \203\275�\n\204\275�\320\321\"\210\322@8\206\334�\304 8\206\334�\304\303 \3158\"8\206\334�\3238\262\303\"\262 \304@8\206\314 8\206\3248\206\314\303 \3158\"8\206\314 8\206\304 8@@\262\303\3048\"\262\f\323@8\206*\3258\262 A@\3228\3048B@\206C\3148A@\3228B@\206TA@\3228B@\206eA@\3228B\257\n\262\n\326 \3238T\306\"B&\n\262\327  C\n#\262 A\262\202W�\203\321\306\211@A@\3228B@A@\3228B\306\211\211S\257\n B\262 \307U\204\344\203\350\330U\203\350\310\317!\210+\207" [ent-alist conf-alist conf-key vhdl-aget 3 last nil 0 message "Extract design hierarchy..." error "ERROR: Instantiation loop detected, component instantiates itself: \"%s\"" 4 7 "all" "" vhdl-warning-when-idle "Configuration not found: \"%s\"" 2 5 6 8 vhdl-get-hierarchy append 1] 39 (#$ . 436583)])#@64 Get all instantiations of entity ENT-KEY. (fn ENT-KEY INDENT) (defalias 'vhdl-get-instantiations #[514 "\303\304!\"\305\211\211\211\211\211\211\203x�\n@\262\3068\211\203q� @\262\3068\262\203j�@\262\3078\232\203c�\211A@\3108\3118BA@\3108\3118BA@\3108\3118B\257B\262A\262\202*� A\211\204!�\nA\211\204�\237*\207" [vhdl-entity-alist arch-alist ent-alist vhdl-aget vhdl-speedbar-line-key nil 4 5 2 3] 18 (#$ . 438092)])#@44 Save all updated hierarchy caches to file. (defalias 'vhdl-save-caches #[0 "\3021'�\205%�\303 \210 \304\305!\210\211\203 �\306@!\210\211A\262\202�\304\307!\2620\207\210\310\311!\210\312\313!\207" [vhdl-speedbar-save-cache vhdl-updated-project-list (error) vhdl-update-hierarchy message "Saving hierarchy caches..." vhdl-save-cache "Saving hierarchy caches...done" vhdl-warning "ERROR: An error occurred while saving the hierarchy caches" sit-for 2] 3 (#$ . 438553) nil])#@49 Save current hierarchy cache to file. (fn KEY) (defalias 'vhdl-save-cache #[257 "p\306 \307\310 !\311\312\313\nB\314\315\316\206�\317#\320\321 Q\"!\322\"\206)�\2031�\323\2022�\324\325\326!!\204A�\327\326!\330\"\210\331!\204W�\332\333\334\307!\"!\210\335\336!\202k\337\340\"\210\341\330\211#q\210\342 \210\343\344\345!\346 \347\261\210\350\203|�\351\202}�\352\353\261\210\203\213�c\210\202\220�\354p\"\210\355\356\357!\321 \360\361\362 \363\350\203\245�\323\202\246�\324\364\365\f\320\261\210\354\206\265�p\"\210\366c\210\367\f>\2035\370\371\372\261\210\373\374 \"p\"\210\375\376\372\261\210\373\374@\"p\"\210\377\201G�\372\261\210\373\374A\"p\"\210\201H�\201I�\372\261\210\373\374B\"p\"\210\201J�\201K�\372\261\210\373\374C\"p\"\210\2032\201L�\201M�\372\261\210\373\374D\"p\"\210\366c\210\201N�\f>\203T\201O�\201P�\372\261\210\373\374E\"p\"\210\366c\210\201Q�F\"F\201R� \210\201S�p!\210q*\207" [vhdl-project default-directory vhdl-speedbar-cache-file-name vhdl-version vhdl-speedbar-save-cache vhdl-entity-alist vhdl-project-p abbreviate-file-name vhdl-default-directory vhdl-resolve-env-variable vhdl-replace-string "\\(.*\\) \\(.*\\)" subst-char-in-string 32 95 "dir" " " user-login-name expand-file-name "project" "directory" file-exists-p file-name-directory make-directory t file-writable-p vhdl-warning format "File not writable: \"%s\"" sit-for 2 message "Saving cache: \"%s\"" find-file-noselect erase-buffer ";; -*- Emacs-Lisp -*-\n\n" ";;; " file-name-nondirectory " - design hierarchy cache file for Emacs VHDL Mode " "\n" "\n;; " "Project " "Directory" " : " prin1 "\n;; Saved : " format-time-string "%Y-%m-%d %T " "\n\n" "\n;; version number\n" "(setq vhdl-cache-version \"" "\")\n" " name" "\n(setq " ")\n" hierarchy "\n;; entity and architecture cache\n" "(vhdl-aput 'vhdl-entity-alist " " '" print vhdl-aget ")\n\n;; configuration cache\n" "(vhdl-aput 'vhdl-config-alist " ")\n\n;; package cache\n" vhdl-config-alist vhdl-package-alist vhdl-ent-inst-alist vhdl-file-alist vhdl-directory-alist vhdl-speedbar-shown-unit-alist vhdl-updated-project-list "(vhdl-aput 'vhdl-package-alist " ")\n\n;; instantiated entities cache\n" "(vhdl-aput 'vhdl-ent-inst-alist " ")\n\n;; design units per file cache\n" "(vhdl-aput 'vhdl-file-alist " ")\n\n;; source directories in project cache\n" "(vhdl-aput 'vhdl-directory-alist " display "\n;; shown design units cache\n" "(vhdl-aput 'vhdl-speedbar-shown-unit-alist " delete save-buffer kill-buffer] 22 (#$ . 439035)])#@55 Load hierarchy cache information from file. (fn KEY) (defalias 'vhdl-load-cache #[257 "\211\211\305 \306\307\310\nB\311\312\313\314 \206�\315#\316\317 Q\"!\320\"\321\322\f>\204,�\323\304\322\"\210\324!\205X�\3251O�\326!\210\327\330\331\332\333\"\334#\327\335\331 \333\"\334#\2310\202X�\210\336\337\340\"!\210\321+\207" [vhdl-project default-directory vhdl-speedbar-cache-file-name vhdl-cache-version kill-emacs-hook vhdl-default-directory vhdl-resolve-env-variable vhdl-replace-string "\\(.*\\) \\(.*\\)" subst-char-in-string 32 95 vhdl-project-p "dir" " " user-login-name expand-file-name nil vhdl-save-caches add-hook file-exists-p (error) load-file mapconcat #[257 "\300\301\302!\"\207" [format "%3d" string-to-number] 5 "\n\n(fn A)"] split-string "3.33" "\\." "" #[257 "\300\301\302!\"\207" [format "%3d" string-to-number] 5 "\n\n(fn A)"] vhdl-warning format "ERROR: Corrupted cache file: \"%s\""] 10 (#$ . 441587)])#@91 Make sure that hierarchy information is available. Load cache or scan files if required. (defalias 'vhdl-require-hierarchy-info #[0 "\303 \203�\304 \"\206�\305!?\205-�\306!\207\307\n!\304 \"\206$�\305!?\205+�\310!\262\207" [vhdl-project vhdl-file-alist default-directory vhdl-project-p assoc vhdl-load-cache vhdl-scan-project-contents abbreviate-file-name vhdl-scan-directory-contents] 4 (#$ . 442526)])#@54 Keymap used when in the VHDL hierarchy browser mode. (defvar vhdl-speedbar-mode-map nil (#$ . 442945))#@49 Additional menu-items to add to speedbar frame. (defvar vhdl-speedbar-menu-items nil (#$ . 443053))#@22 Initialize speedbar. (defalias 'vhdl-speedbar-initialize #[0 "\211\203�\211@A\306=\203�\307@@!\210\211A\262\202�\210\310\311!\205\201\312\313!\210\312\314!\210 \204\234�\315 \316 \317\320#\210\316 \321\320#\210\316 \322\323#\210\316 \324\323#\210\316 \325\326#\210\316 \327\330#\210\316 \331\332#\210\316 \333\334#\210\316 \335\336#\210\316 \337\340#\210\316 \341\342#\210\316 \343\344#\210\316 \345\346#\210\347\211\350X\203\233�\316 \351!\352\353\354\355DF#\210\211T\262\202�\210\316\n\356\357#\210\316\n\360\361#\210 \204D\362\363\364\365\366\347\367\350X\203\344�\370\347U\203\304�\371\202\307�\351!\355D\372\373\374\375\376 E\377\351\n!&B\262T\262\202\263�\211\237\266\202\201A�\201B�\201C�\201D�\201E�\201F�\201G�\201H�\370\201I�\344\201J�\201K�\201L�\201M�BBBBB\"\201H�\370\201N�\344\201J�\201O�\201L�\201P�BBBBB\"\201Q�BBBBBBBBBBBBBBB\201R�\201S�!\210\201R�\201T�!\210\201U�\201V�\f\" \201W�=\203j\201X�@ \201Y�=\203w\201Z�@\201[�\201\\�\201]�\"\207" [auto-mode-alist vhdl-speedbar-mode-map speedbar-mode-map vhdl-speedbar-menu-items speedbar-stealthy-function-list vhdl-speedbar-display-mode vhdl-mode speedbar-add-supported-extension boundp speedbar-mode-functions-list speedbar-add-mode-functions-list ("vhdl directory" (speedbar-item-info . vhdl-speedbar-item-info) (speedbar-line-directory . speedbar-files-line-directory)) ("vhdl project" (speedbar-item-info . vhdl-speedbar-item-info) (speedbar-line-directory . vhdl-speedbar-line-project)) speedbar-make-specialized-keymap define-key "e" speedbar-edit-line " " "+" speedbar-expand-line "=" "-" vhdl-speedbar-contract-level "_" vhdl-speedbar-contract-all "C" vhdl-speedbar-port-copy "P" vhdl-speedbar-place-component "F" vhdl-speedbar-configuration "A" vhdl-speedbar-select-mra "K" vhdl-speedbar-make-design "R" vhdl-speedbar-rescan-hierarchy "S" vhdl-save-caches 0 9 int-to-string lambda nil (interactive) vhdl-speedbar-set-depth "h" #[0 "\300\301!\207" [speedbar-change-initial-expansion-list "vhdl directory"] 2 nil nil] "H" #[0 "\300\301!\207" [speedbar-change-initial-expansion-list "vhdl project"] 2 nil nil] ["Edit" speedbar-edit-line t] ["Expand" speedbar-expand-line (save-excursion (beginning-of-line) (looking-at "[0-9]+: *.\\+. "))] ["Contract" vhdl-speedbar-contract-level t] ["Expand All" vhdl-speedbar-expand-all t] ["Contract All" vhdl-speedbar-contract-all t] ("Hierarchy Depth") vector "All" :style radio :selected = vhdl-speedbar-hierarchy-depth :keys speedbar-initial-expansion-list-name "--" ["Copy Port/Subprogram" vhdl-speedbar-port-copy (or (vhdl-speedbar-check-unit 'entity) (vhdl-speedbar-check-unit 'subprogram))] ["Place Component" vhdl-speedbar-place-component (vhdl-speedbar-check-unit 'entity)] ["Generate Configuration" vhdl-speedbar-configuration (vhdl-speedbar-check-unit 'architecture)] ["Select as MRA" vhdl-speedbar-select-mra (vhdl-speedbar-check-unit 'architecture)] ["Make" vhdl-speedbar-make-design (save-excursion (beginning-of-line) (looking-at "[0-9]+: *[[<]"))] ["Generate Makefile" vhdl-speedbar-generate-makefile (save-excursion (beginning-of-line) (looking-at "[0-9]+:"))] apply "Rescan Directory" :active (save-excursion (beginning-of-line) (looking-at "[0-9]+:")) :visible ((not vhdl-speedbar-show-projects)) "Rescan Project" (save-excursion (beginning-of-line) (looking-at "[0-9]+:")) (vhdl-speedbar-show-projects) (["Save Caches" vhdl-save-caches vhdl-updated-project-list]) speedbar-add-expansion-list ("vhdl directory" vhdl-speedbar-menu-items vhdl-speedbar-mode-map vhdl-speedbar-display-directory) ("vhdl project" vhdl-speedbar-menu-items vhdl-speedbar-mode-map vhdl-speedbar-display-projects) append (("vhdl directory" vhdl-speedbar-update-current-unit) ("vhdl project" vhdl-speedbar-update-current-project vhdl-speedbar-update-current-unit)) directory "vhdl directory" project "vhdl project" add-hook speedbar-timer-hook vhdl-update-hierarchy] 22 (#$ . 443158)])#@42 Open/close speedbar. (fn &optional ARG) (defalias 'vhdl-speedbar #[256 "\300\301!\204\n�\302\303!\207\3041�\305!0\207\210\302\306!\207" [fboundp speedbar error "WARNING: Speedbar is not available or not installed" (error) speedbar-frame-mode "WARNING: An error occurred while opening speedbar"] 3 (#$ . 447080) nil])#@32 Name of last selected project. (defvar vhdl-speedbar-last-selected-project nil (#$ . 447407))#@97 Display directory and hierarchy information in speedbar. (fn DIRECTORY DEPTH &optional RESCAN) (defalias 'vhdl-speedbar-display-directory #[770 "\306\307 !\310\311!!\262\306\312\31314�\314\"\210\315\316!\"\210\317 #\210\320U\2050�\321!0\2028�\210\322\323!)\207" [vhdl-speedbar-show-projects speedbar-ignored-directory-expressions speedbar-ignored-directory-regexp speedbar-last-selected-file inhibit-read-only speedbar-power-click nil speedbar-extension-list-to-regex abbreviate-file-name file-name-as-directory t (error) speedbar-directory-buttons vhdl-speedbar-insert-dirs speedbar-file-lists vhdl-speedbar-insert-dir-hierarchy 0 vhdl-speedbar-expand-dirs vhdl-warning-when-idle "ERROR: Invalid hierarchy information, unable to display correctly"] 7 (#$ . 447506)])#@94 Display projects and hierarchy information in speedbar. (fn PROJECT DEPTH &optional RESCAN) (defalias 'vhdl-speedbar-display-projects #[770 "\306\307\310\211\306\3111�\312 0\210\202�\210\313\314!\210)\310\211\207" [vhdl-speedbar-show-projects speedbar-ignored-directory-regexp speedbar-last-selected-file vhdl-speedbar-last-selected-project inhibit-read-only speedbar-full-text-cache t "." nil (error) vhdl-speedbar-insert-projects vhdl-warning-when-idle "ERROR: Invalid hierarchy information, unable to display correctly"] 6 (#$ . 448295)])#@34 Insert all projects in speedbar. (defalias 'vhdl-speedbar-insert-projects #[0 "\304\305!\210\203�\306\307 !!\202� \310\211\2032�\311\312\313\314@@@@\315@@\316\317& \210\211A\262\202� \262\211\205_�\211@@ \235\203X�eb\210\320\321@@\322Q\310\323#\203X�\324\225b\210\325 \210\211A\262\2025�)\207" [vhdl-project-sort vhdl-project-alist vhdl-speedbar-update-current-unit vhdl-speedbar-shown-project-list vhdl-speedbar-make-title-line "Projects:" vhdl-sort-alist copy-alist nil speedbar-make-tag-line angle 43 vhdl-speedbar-expand-project vhdl-toggle-project speedbar-directory-face 0 re-search-forward "^\\([0-9]+:\\s-*<\\)[+]>\\s-+" "$" t 1 speedbar-do-function-pointer] 11 (#$ . 448852)])#@154 Insert hierarchy of PROJECT. Rescan directories if optional argument RESCAN is non-nil, otherwise use cached data. (fn PROJECT INDENT &optional RESCAN) (defalias 'vhdl-speedbar-insert-project-hierarchy #[770 "\211\204�\305\"\204�\306!\204�\307!\210\310\311 \"\311\n\"\311 \"\311\f\"@%\210\312!\313\261\210\314`\315Z`S\316\317$\210\314`S`\316\320$\210\321!\207" [vhdl-file-alist vhdl-entity-alist vhdl-config-alist vhdl-package-alist vhdl-ent-inst-alist assoc vhdl-load-cache vhdl-scan-project-contents vhdl-speedbar-insert-hierarchy vhdl-aget int-to-string ":\n" put-text-property 3 invisible t nil vhdl-speedbar-expand-units] 10 (#$ . 449557)])#@155 Insert hierarchy of DIRECTORY. Rescan directory if optional argument RESCAN is non-nil, otherwise use cached data. (fn DIRECTORY DEPTH &optional RESCAN) (defalias 'vhdl-speedbar-insert-dir-hierarchy #[770 "\211\204�\305\"\204�\306!\204�\307!\210\310\311 \"\311\n\"\311 \"\311\f\"@%\210\312!\210\313\314\211CC#\207" [vhdl-file-alist vhdl-entity-alist vhdl-config-alist vhdl-package-alist vhdl-ent-inst-alist assoc vhdl-load-cache vhdl-scan-directory-contents vhdl-speedbar-insert-hierarchy vhdl-aget vhdl-speedbar-expand-units vhdl-aput vhdl-directory-alist] 10 (#$ . 450229)])#@140 Insert hierarchy of ENT-ALIST-ARG, CONF-ALIST-ARG, and PACKAGE-ALIST. (fn ENT-ALIST-ARG CONF-ALIST-ARG PACKAGE-ALIST ENT-INST-LIST DEPTH) (defalias 'vhdl-speedbar-insert-hierarchy #[1285 "\204�\204�\204�\303\304\"\207\305\211\211\211\203&�\303\306\"\210\n\203p�\n@\262\307\310\311\312@A@\313\314\n8\315 8B\316& \210\3148\204X�\317\210\320c\210\321u\210@\235\204i�\317\210\322c\210\321u\210\nA\211\204*� \203z�\303\323\"\210 \203\237� @\307\310\311\324@A@\313\3148\3158B\325& \210 A\211\204~�\203\252�\303\326\"\210\205\325�@\262\327@A@\3148\3158B\3308\3318B\n%\210A\262\202\252�+\207" [conf-entry conf-alist ent-alist vhdl-speedbar-make-title-line "No VHDL design units!" nil "Entities:" speedbar-make-tag-line bracket 43 vhdl-speedbar-expand-entity vhdl-speedbar-find-file 2 3 vhdl-speedbar-entity-face 0 "!" 1 " (top)" "Configurations:" vhdl-speedbar-expand-config vhdl-speedbar-configuration-face "Packages:" vhdl-speedbar-make-pack-line 7 8] 21 (#$ . 450831)])#@65 Rescan hierarchy for the directory or project under the cursor. (defalias 'vhdl-speedbar-rescan-hierarchy #[0 "\301\211\203�\302 \262\303!\210\202>�\212\304 \210\305\306!)\203,�\307\310\301\311#\210\312\313\314 !!\210\202>�\314 \262\315\316\"\210\312\313\317\320\"!!\210\321!\207" [vhdl-speedbar-show-projects nil vhdl-speedbar-line-project vhdl-scan-project-contents beginning-of-line looking-at "[^0-9]" re-search-forward "[0-9]+:" t vhdl-scan-directory-contents abbreviate-file-name speedbar-line-directory string-match "^\\(.+[/\\]\\)" match-string 1 vhdl-speedbar-refresh] 7 (#$ . 451865) nil])#@95 Expand subdirectories in DIRECTORY according to `speedbar-shown-directories'. (fn DIRECTORY) (defalias 'vhdl-speedbar-expand-dirs #[257 "\303!A\304\305\n!C\211\203-�\306@!\203&�\307 \210\310\311!\203&�\312\225b\210\313 \210\211A\262\202 �)\210\301\304\314\"\207" [speedbar-shown-directories vhdl-speedbar-update-current-unit default-directory reverse nil expand-file-name speedbar-goto-this-file beginning-of-line looking-at "[0-9]+:\\s-*<" 0 speedbar-do-function-pointer t] 4 (#$ . 452478)])#@103 Expand design units in directory/project KEY according to `vhdl-speedbar-shown-unit-alist'. (fn KEY) (defalias 'vhdl-speedbar-expand-units #[257 "\306\"\307\211\310\300\"\210\311\312 p\313\314#\216\315 !\210 \203\204�\316 @@\"\210\317 \210 @A@\307\320\321!\203{�\322\225b\210`\262\323 \210\324!\210\203{�\211b\210\325\326@\327Q\307\311#\203r�\317 \210\320\330!\203r�\322\225b\210\323 \210\324!\210A\211\204M� A)\266\202�-\266\302\307\311\"\207" [vhdl-speedbar-shown-unit-alist vhdl-updated-project-list vhdl-speedbar-update-current-unit unit-alist case-fold-search vhdl-mode-ext-syntax-table vhdl-aget nil vhdl-adelete t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table vhdl-speedbar-goto-this-unit beginning-of-line looking-at "^[0-9]+:\\s-*\\[" 0 speedbar-do-function-pointer select-frame re-search-forward "^[0-9]+:\\s-*\\(\\[\\|{.}\\s-+" "\\>\\)" "^[0-9]+:\\s-*{" arch-alist speedbar-frame] 10 (#$ . 452983)])#@54 Contract current level in current directory/project. (defalias 'vhdl-speedbar-contract-level #[0 "\212\300 \210\301\302!)\204(�\212\300 \210\301\303!)\2051�\304\305\306\307\310\311!!S\312]\"\313\314#\2051�\312\225b\210\315 \210\316 \207" [beginning-of-line looking-at "^[0-9]:\\s-*[[{<]-" "^\\([0-9]+\\):" re-search-backward format "^[0-%d]:\\s-*[[{<]-" string-to-number match-string 1 0 nil t speedbar-do-function-pointer speedbar-center-buffer-smartly] 6 (#$ . 453986) nil])#@66 Contract all expanded design units in current directory/project. (defalias 'vhdl-speedbar-contract-all #[0 "\203�\212\304 \210\305\306!)\203�\307\310 \207\311 \312\313\"\210\310\205!�!\210\314\n>\2056�\211 \235\2031� \207\211 B\211\207" [vhdl-speedbar-show-projects vhdl-speedbar-shown-project-list vhdl-speedbar-save-cache vhdl-updated-project-list beginning-of-line looking-at "^0:" nil vhdl-speedbar-refresh vhdl-speedbar-line-key vhdl-adelete vhdl-speedbar-shown-unit-alist display] 4 (#$ . 454468) nil])#@55 Expand all design units in current directory/project. (defalias 'vhdl-speedbar-expand-all #[0 "\306 \307\"\307\n\"\307\f\"\310\211\310\235\203%�\210\202+�B \203_�\311 @8\310\262\203N�@@B\262A\211\204=� @@DB A\211\204/� \203s� @@CB A\211\204c� \203\207� @@CB A\211\204w�\312\313#\210\314 \210\315>\205\253�\235\203\244�\202\253�B\211-\207" [vhdl-entity-alist ent-alist vhdl-config-alist conf-alist vhdl-package-alist pack-alist vhdl-speedbar-line-key vhdl-aget nil 4 vhdl-aput vhdl-speedbar-shown-unit-alist vhdl-speedbar-refresh display arch-alist unit-alist vhdl-speedbar-shown-project-list vhdl-speedbar-save-cache vhdl-updated-project-list] 7 (#$ . 454990) nil])#@71 Expand/contract the project under the cursor. (fn TEXT TOKEN INDENT) (defalias 'vhdl-speedbar-expand-project #[771 "\304\305\"\203)�\306\307!\210\235\204�B\310\212\311\210\312u\210\313T\n#*\210\202D�\304\314\"\203@�\306\315!\210\316\"\317!\210\202D�\320\321!\210\322 \232\205M�\323 \207" [vhdl-speedbar-shown-project-list inhibit-read-only speedbar-power-click speedbar-frame string-match "\\+" speedbar-change-expand-button-char 45 t nil 1 vhdl-speedbar-insert-project-hierarchy "-" 43 delete speedbar-delete-subblock error "Nothing to display" selected-frame speedbar-center-buffer-smartly] 7 (#$ . 455726)])#@70 Expand/contract the entity under the cursor. (fn TEXT TOKEN INDENT) (defalias 'vhdl-speedbar-expand-entity #[771 "\306\307\"\203\310!\311\"\311 \"\3128\313\"\3148\nG\315V\316\211\n\2047�\2047�\2047�\317\320!\210\202 \317\321!\210\311 \"\322\304\n\316#\210\322\303\f#)\210\323\212\316\210\315u\210\n\203d�\324\325 T\"\210\n\203\251�\n@\262\326\327\330\331\f@BA@\332\333 8\312\n8B\334T& \210\203\242�@\3358\232\203\242�\336\210\337c\210\315u\210\nA\211\204h�\203\264�\324\340 T\"\210\203\342�@\262\341@A@\3338\3128\3358\3148\316\211\211T\336\342&\f\210A\262\202\264�\343 T\n#*\210\344->\203.\235\203.\210\202.B.\345\323\211\"\210*\266\202d\306\346\"\203`\317\330!\210\310!\311 \"\347\304\"\210\f\2038\322\303\f#\210\202=\347\303\"\210\350!\210\344->\203[\211.\235\203U.\210\202[\211.B.)\210\202d\351\352!\210\353 /\232\205n\354 \207" [vhdl-entity-alist ent-alist arch-alist vhdl-speedbar-shown-unit-alist unit-alist inhibit-read-only string-match "\\+" vhdl-speedbar-line-key vhdl-aget 3 vhdl-get-instantiations 5 1 nil speedbar-change-expand-button-char 63 45 vhdl-aput t vhdl-speedbar-make-title-line "Architectures:" speedbar-make-tag-line curly 43 vhdl-speedbar-expand-architecture vhdl-speedbar-find-file 2 vhdl-speedbar-architecture-face 4 0 " (mra)" "Instantiated as:" vhdl-speedbar-make-inst-line " in " vhdl-speedbar-insert-subpackages display vhdl-speedbar-update-current-unit "-" vhdl-adelete speedbar-delete-subblock error "Nothing to display" selected-frame speedbar-center-buffer-smartly vhdl-speedbar-save-cache vhdl-updated-project-list speedbar-frame] 24 (#$ . 456360)])#@76 Expand/contract the architecture under the cursor. (fn TEXT TOKEN INDENT) (defalias 'vhdl-speedbar-expand-architecture #[771 "\306\307\"\203\376�\310S!\311\"\311\n\"\312 @A\313\211\314 S&\311 @\"\311\3158A\"\3168\313\204E�\204E�\317\320!\210\202\370�\317\321!\210\311\f\"\311  @\"@*\322\305 @\nA*BC#\210\322\304 #*\210\323+\212\313\210\324u\210\203\203�\325\326T\"\210\203\316�@\262,\314U\204\233�\3278,W\203\307�\330@A@\3318\3158\3168\3328\3338\334 8\335\n8T\327\f8T\336&\f\210A\262\202\203�\337T S#*\210\340->\203\363�.\235\203\355�.\210\202\363�.B.\341\323\211\"\210*\266\202U\306\342\"\203Q\317\343!\210\310S!\311\f\"\311 @\"@*\322\305@\344A*\"C#\210\322\304 #\210\345!\210\340->\203L\211.\235\203F.\210\202L\211.B.*\210\202U\346\347!\210\350 /\232\205_\351 \207" [vhdl-entity-alist ent-alist vhdl-config-alist conf-alist vhdl-speedbar-shown-unit-alist unit-alist string-match "\\+" vhdl-speedbar-line-key vhdl-aget vhdl-get-hierarchy nil 0 3 4 speedbar-change-expand-button-char 63 45 vhdl-aput t 1 vhdl-speedbar-make-title-line "Subcomponent hierarchy:" 9 vhdl-speedbar-make-inst-line 2 5 6 7 8 ": " vhdl-speedbar-insert-subpackages display vhdl-speedbar-update-current-unit "-" 43 delete speedbar-delete-subblock error "Nothing to display" selected-frame speedbar-center-buffer-smartly arch-alist inhibit-read-only vhdl-speedbar-hierarchy-depth vhdl-speedbar-save-cache vhdl-updated-project-list speedbar-frame] 22 (#$ . 458052)])#@77 Expand/contract the configuration under the cursor. (fn TEXT TOKEN INDENT) (defalias 'vhdl-speedbar-expand-config #[771 "\306\307\"\203\347�\310!\311\"\311 \"\311 \"\312\f \313\n8\314\n8\315\n8\316 \317& \320\n8\321\204@�\204@�\322\323!\210\202\341�\322\324!\210\311 \"\325\326\321#\210\325\305#)\210\317+\212\321\210\327u\210\203n�\330\331T\"\210\203\270�@\262,\316U\204\206�\3328,X\203\261�\333@A@\3348\3138\3148\3158\3208\335 8\336\n8T\332\f8\337&\f\210A\262\202n�\340T#*\210\341->\203\334�.\235\203\326�.\210\202\334�.B.\342\317\211\"\210+\266\202;\306\343\"\2037\322\344!\210\310!\311 \"\345\326\"\210\203\325\305#\210\202\345\305\"\210\346!\210\341->\2032\211.\235\203,.\210\2022\211.B.)\210\202;\347\350!\210\351 /\232\205E\352 \207" [vhdl-config-alist conf-alist conf-entry vhdl-entity-alist ent-alist vhdl-speedbar-shown-unit-alist string-match "\\+" vhdl-speedbar-line-key vhdl-aget vhdl-get-hierarchy 3 4 5 0 t 6 nil speedbar-change-expand-button-char 63 45 vhdl-aput unit-alist 1 vhdl-speedbar-make-title-line "Design hierarchy:" 9 vhdl-speedbar-make-inst-line 2 7 8 ": " vhdl-speedbar-insert-subpackages display vhdl-speedbar-update-current-unit "-" 43 vhdl-adelete speedbar-delete-subblock error "Nothing to display" selected-frame speedbar-center-buffer-smartly inhibit-read-only vhdl-speedbar-hierarchy-depth vhdl-speedbar-save-cache vhdl-updated-project-list speedbar-frame] 20 (#$ . 459591)])#@71 Expand/contract the package under the cursor. (fn TEXT TOKEN INDENT) (defalias 'vhdl-speedbar-expand-package #[771 "\306\307\"\203 \310!\311\"\311 \"\3128\3138\3148\315\3168\3178\"\320\211\211\204<�\204<�\204<�\321\322!\210\202\321\323!\210\311\n\n\"\324\303\f\320#\210\324\302\n #)\210\325\212\320\210\326u\210\203j�\327\330 T\"\210\203\233�@\262\331\320\211\211@BA@\332\333\n8\312 8B\334T& \210A\262\202j�\203\246�\327\335 T\"\210\203\331�@\262\311@\"\262\3338\203\322�\336A@\3338\3128BA@\3338B T$\210A\262\202\246�\337 T\f#*\210\340 >\203\376�*\235\203\367�*\210\202\376�*B*\341\325\211\"\210)\266 \202Y\306\342\"\203U\321\343!\210\310!\311\n\"\344\303\"\210 \203.\324\302 #\210\2023\344\302\"\210\345!\210\340 >\203P\211*\235\203J*\210\202P\211*B*)\210\202Y\346\347!\210\350 +\232\205c\351 \207" [vhdl-package-alist pack-alist vhdl-speedbar-shown-unit-alist unit-alist inhibit-read-only vhdl-speedbar-save-cache string-match "\\+" vhdl-speedbar-line-key vhdl-aget 3 4 8 append 5 9 nil speedbar-change-expand-button-char 63 45 vhdl-aput t 1 vhdl-speedbar-make-title-line "Components:" speedbar-make-tag-line vhdl-speedbar-find-file 2 vhdl-speedbar-entity-face "Subprograms:" vhdl-speedbar-make-subprogram-line vhdl-speedbar-insert-subpackages display vhdl-speedbar-update-current-unit "-" 43 vhdl-adelete speedbar-delete-subblock error "Nothing to display" selected-frame speedbar-center-buffer-smartly vhdl-updated-project-list speedbar-frame] 22 (#$ . 461101)])#@65 Insert required packages. (fn SUBPACK-ALIST INDENT DIR-INDENT) (defalias 'vhdl-speedbar-insert-subpackages #[771 "\302\303!\"\304\211\211\203�\305\306\"\210\205J�@A\262@@\262\302 \"\262\307@\206/�A@\3108B\3118\3128B %\210A\262\202�)\207" [vhdl-package-alist pack-alist vhdl-aget vhdl-speedbar-line-key nil vhdl-speedbar-make-title-line "Packages Used:" vhdl-speedbar-make-subpack-line 2 6 7] 13 (#$ . 462670)])#@59 Non-nil means to run `vhdl-speedbar-update-current-unit'. (defvar vhdl-speedbar-update-current-unit t (#$ . 463113))#@45 Highlight project that is currently active. (defalias 'vhdl-speedbar-update-current-project #[0 "\203o� \n\232\204o�\306\303!\203o�\307 !\203o�\310 \f\311\312 !\210\313\212\203^�eb\210\314\315@@\316Q\311\313#\203W�\317\320\224\320\225\321@@\n\232\203G�\322\202H�\323$\210@@\n\232\203W�\320\224S\262A\262\202!�)\211\203f�\211b\210)\312!\210\n\266\313\207" [vhdl-speedbar-show-projects vhdl-speedbar-last-selected-project vhdl-project speedbar-frame vhdl-project-alist inhibit-read-only boundp frame-live-p selected-frame nil select-frame t re-search-forward "<.> \\(" "\\)$" put-text-property 1 face speedbar-selected-face speedbar-directory-face] 9 (#$ . 463235)])#@156 Highlight all design units that are contained in the current file. NO-POSITION non-nil means do not re-position cursor. (fn &optional NO-POSITION ALWAYS) (defalias 'vhdl-speedbar-update-current-unit #[512 "\306 \307\211\211\310\311!\203�\312\313\314\315\"!\210\202�\316\n!\210\317\320 \206#�\321!\262 \203\2044�\211\f\232\204 \203N�\203W�\322 \3230@\"\"A\262\2028�\3230\3171!\"\316\f!\2102q\210\324\21134\325 p\326\327#\216\3305!\210\212\323 \f\"\331\332@\f\333$\210\331\334A@\f\335$\210\331\332\3368\f\337$\210\331\340\3418\f\342$\210\331\343\344\f\342$\210\331\345\3468\f\347$\266\323 \"\331\332@\350\307%\262\331\334A@\351 %\262\331\332\3368\352 %\262\331\340\3418\353 %\262\331\343\354\353 %\262\331\345\3468\355 %,\262\266\203\204b\210\356 \210\357 \210\211\316!)\210\324\207" [vhdl-speedbar-shown-project-list file-alist speedbar-attached-frame vhdl-speedbar-update-current-unit speedbar-last-selected-file vhdl-speedbar-show-projects selected-frame nil fboundp speedbar-select-attached-frame dframe-select-attached-frame dframe-current-frame speedbar-frame speedbar-mode select-frame abbreviate-file-name buffer-file-name "" append vhdl-aget t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table vhdl-speedbar-update-units "\\[.] " vhdl-speedbar-entity-face "{.} " vhdl-speedbar-architecture-face 3 vhdl-speedbar-configuration-face "[]>] " 4 vhdl-speedbar-package-face "\\[.].+(" ("body") "> " 6 vhdl-speedbar-instantiation-face vhdl-speedbar-entity-selected-face vhdl-speedbar-architecture-selected-face vhdl-speedbar-configuration-selected-face vhdl-speedbar-package-selected-face ("body") vhdl-speedbar-instantiation-selected-face speedbar-center-buffer-smartly speedbar-position-cursor-on-line vhdl-file-alist default-directory speedbar-buffer inhibit-read-only case-fold-search vhdl-mode-ext-syntax-table] 17 (#$ . 463918)])#@92 Help function to highlight design units. (fn TEXT UNIT-LIST FILE-NAME FACE &optional POS) (defalias 'vhdl-speedbar-update-units #[1284 "\203;�eb\210\300\301@\302R\303\304#\2034�\305\306\224\307\"@\232\203�\211\206&�\310 \262\311\306\224\306\225\312$\210\202�A\262\202��\207" [re-search-forward "\\(" "\\)\\>" nil t get-text-property 1 speedbar-token point-marker put-text-property face] 10 (#$ . 465885)])#@173 Insert instantiation entry. (fn INST-NAME INST-FILE-MARKER ENT-NAME ENT-FILE-MARKER ARCH-NAME ARCH-FILE-MARKER CONF-NAME CONF-FILE-MARKER LIB-NAME DEPTH OFFSET DELIMITER) (defalias 'vhdl-speedbar-make-inst-line #[3084 "`\301\302!\303\261\210\304`\305\306$\210`\262\307\310_\"\210\311V\203;�\312c\210\307\313U\203/�\314\2020�\310S\"\210S\262\202�\304`\305\301$\210`\262\315c\210\316`\301\211\211%\210`\262\317c\210`\262 \204d�\320c\210\202s� c\210\316`\321\322\323&\210c\210 \203\307�`\262 c\210\316`\324\322\323&\210 \203\252�\325c\210`\262 c\210\316`\326\322\323&\210\327c\210\203\307�\325c\210`\262c\210\316`\330\322\323\f&\210\327c\210\203\347�\331 \227\232\204\347�`\262\325\327\261\210\304\332\\`S\333\334$\210\307\335\313\"\210\304`\305\301$\207" [speedbar-indentation-width nil int-to-string ":" put-text-property invisible t insert-char 32 0 "|" 1 45 ">" speedbar-make-button " " "(top)" vhdl-speedbar-instantiation-face speedbar-highlight-face vhdl-speedbar-find-file vhdl-speedbar-entity-face " (" vhdl-speedbar-architecture-face ")" vhdl-speedbar-configuration-face vhdl-work-library 2 face vhdl-speedbar-library-face 10] 21 (#$ . 466309)])#@88 Insert package entry. (fn PACK-KEY PACK-NAME PACK-FILE-MARKER BODY-FILE-MARKER DEPTH) (defalias 'vhdl-speedbar-make-pack-line #[1285 "`\301\302!\303\261\210\304`\305\306$\210`\262\307\310_\"\210\304`\305\301$\210`\262\311c\210\312`\313\314\315\f&\210`\262\307\310\316\301#\210`\262c\210\312`\317\314\320\n&\210@\204T�\321c\210@\203p�\322c\210`\262\323c\210\312`\317\314\320 &\210\324c\210\307\325\316\"\210\304`\305\301$\207" [speedbar-indentation-width nil int-to-string ":" put-text-property invisible t insert-char 32 "[+]" speedbar-make-button speedbar-button-face speedbar-highlight-face vhdl-speedbar-expand-package 1 vhdl-speedbar-package-face vhdl-speedbar-find-file "!" " (" "body" ")" 10] 14 (#$ . 467522)])#@98 Insert used package entry. (fn PACK-NAME LIB-NAME PACK-FILE-MARKER PACK-BODY-FILE-MARKER DEPTH) (defalias 'vhdl-speedbar-make-subpack-line #[1285 "`\301\302!\303\261\210\304`\305\306$\210`\262\307\310_\"\210\304`\305\301$\210`\262\311c\210\312`\301\211\211%\210`\262\313c\210`\262c\210\312`\314\315\316\n&\210@\203c�\317c\210`\262\320c\210\312`\314\315\316 &\210\321c\210`\262\317\321\261\210\304\322\\`S\323\324$\210\307\325\326\"\210\304`\305\301$\207" [speedbar-indentation-width nil int-to-string ":" put-text-property invisible t insert-char 32 ">" speedbar-make-button " " vhdl-speedbar-package-face speedbar-highlight-face vhdl-speedbar-find-file " (" "body" ")" 2 face vhdl-speedbar-library-face 10 1] 14 (#$ . 468270)])#@87 Insert subprogram entry. (fn FUNC-NAME FUNC-FILE-MARKER FUNC-BODY-FILE-MARKER DEPTH) (defalias 'vhdl-speedbar-make-subprogram-line #[1028 "`\301\302!\303\261\210\304`\305\306$\210`\262\307\310_\"\210\304`\305\301$\210`\262\311c\210\312`\301\211\211%\210`\262\313c\210`\262c\210\312`\314\315\316\n&\210@\203b�\317c\210`\262\320c\210\312`\314\315\316 &\210\321c\210\307\322\323\"\210\304`\305\301$\207" [speedbar-indentation-width nil int-to-string ":" put-text-property invisible t insert-char 32 ">" speedbar-make-button " " vhdl-speedbar-subprogram-face speedbar-highlight-face vhdl-speedbar-find-file " (" "body" ")" 10 1] 13 (#$ . 469032)])#@60 Insert design unit title entry. (fn TEXT &optional DEPTH) (defalias 'vhdl-speedbar-make-title-line #[513 "`\301\203�\302!\303\261\210\304`\305\306$\210`\262\307\310\206�\311_\"\210`\262c\210\312`\301\211\211\211&\210\307\313\314\"\210\304`\305\301$\207" [speedbar-indentation-width nil int-to-string ":" put-text-property invisible t insert-char 32 0 speedbar-make-button 10 1] 11 (#$ . 469703)])#@42 Insert subdirectories. (fn FILES LEVEL) (defalias 'vhdl-speedbar-insert-dirs #[514 "@\211\205�\300\301\302\303@@\304\305\306\n& \210\211A\262\202�\207" [speedbar-make-tag-line angle 43 vhdl-speedbar-dired speedbar-dir-follow nil speedbar-directory-face] 13 (#$ . 470120)])#@95 Speedbar click handler for directory expand button in hierarchy mode. (fn TEXT TOKEN INDENT) (defalias 'vhdl-speedbar-dired #[771 "\304\305\"\203I�\306\307!\310Q!B\311\312!\210\313 \210\314\212\315\210\316u\210\317\320\307!\310Q!T\"\210\313 \210\321\322\307!\310Q!T\n#*\210\323\314\211\"\210\202\215�\304\324\"\203\211�\313 \210\315\306\307!P!\203y�\304\325\326!P@\"\204r�@B\262A\262\202\\�\237\266\311\327!\210\330!\210\202\215�\331\332!\210\333 \232\205\226�\334 \207" [speedbar-shown-directories inhibit-read-only speedbar-power-click speedbar-frame string-match "\\+" expand-file-name speedbar-line-directory "/" speedbar-change-expand-button-char 45 speedbar-reset-scanners t nil 1 vhdl-speedbar-insert-dirs speedbar-file-lists vhdl-speedbar-insert-dir-hierarchy abbreviate-file-name vhdl-speedbar-update-current-unit "-" "^" regexp-quote 43 speedbar-delete-subblock error "Nothing to display" selected-frame speedbar-center-buffer-smartly] 10 (#$ . 470406)])#@54 Derive and display information about this line item. (defalias 'vhdl-speedbar-item-info #[0 "\212\301 \210\302\303!\203�\304\225b\210\302\305!\203&�\203!�\306\307\310\311!\"\202\275�\312 \202\275�\302\313!\203\272�\311\225b\210\314`\315\"\306\316\317=\204B�\320=\203R�\321\322!\323\232\203N�\324\202\235�\325\202\235�\326=\204^�\327=\203b�\330\202\235�\331=\204n�\332=\203r�\333\202\235�\334=\204~�\335=\203\202�\336\202\235�\337=\204\216�\340=\203\222�\341\202\235�\342=\203\234�\343\202\235�\344\345\302\346!\210\311\224\311\225\"\347\314`\350\"@\206\261�\351\352 \"$\262\202\275�\306\344!)\207" [vhdl-speedbar-show-projects beginning-of-line looking-at "^[0-9]+:" 0 "\\s-*<[-+?]>\\s-+\\([^\n]+\\)$" message "Project \"%s\"" match-string-no-properties 1 speedbar-files-item-info "\\(\\s-*\\([[{][-+?][]}]\\|[| -]*>\\) \\)\"?\\w" get-text-property face "%s \"%s\" in \"%s\"" vhdl-speedbar-entity-face vhdl-speedbar-entity-selected-face match-string 2 ">" "Component" "Entity" vhdl-speedbar-architecture-face vhdl-speedbar-architecture-selected-face "Architecture" vhdl-speedbar-configuration-face vhdl-speedbar-configuration-selected-face "Configuration" vhdl-speedbar-package-face vhdl-speedbar-package-selected-face "Package" vhdl-speedbar-instantiation-face vhdl-speedbar-instantiation-selected-face "Instantiation" vhdl-speedbar-subprogram-face "Subprogram" "" buffer-substring-no-properties "\"?\\(\\(\\w\\|_\\)+\\)\"?" file-relative-name speedbar-token "?" vhdl-default-directory] 9 (#$ . 471407)])#@55 Call `speedbar-line-text' and remove text properties. (defalias 'vhdl-speedbar-line-text #[0 "\300 \301\302G\303$\210\207" [speedbar-line-text set-text-properties 0 nil] 6 (#$ . 472932)])#@41 Get speedbar-line-text of higher level. (defalias 'vhdl-speedbar-higher-text #[0 "\300\211\212\301 \210\302\303!\210\304\305\306!!\262\307\310\311S\"\300\312#\205+�\305\306!\262\313\314G\300$\210\211)\207" [nil beginning-of-line looking-at "^\\([0-9]+\\):" string-to-number match-string 1 re-search-backward format "^%d: *[[<{][-+?][]>}] \\([^ \n]+\\)" t set-text-properties 0] 7 (#$ . 473127)])#@75 Get currently displayed directory of project name. (fn &optional INDENT) (defalias 'vhdl-speedbar-line-key #[256 "\203�\301 \207\302\303\304!!!\207" [vhdl-speedbar-show-projects vhdl-speedbar-line-project abbreviate-file-name file-name-as-directory speedbar-line-directory] 5 (#$ . 473533)])#@62 Get currently displayed project name. (fn &optional INDENT) (defalias 'vhdl-speedbar-line-project #[256 "\205�\212\301\210\302\303\301\304#\210\305\306!)\207" [vhdl-speedbar-show-projects nil re-search-backward "^[0-9]+:\\s-*<[-+?]>\\s-+\\([^\n]+\\)$" t match-string-no-properties 1] 5 (#$ . 473834)])#@40 Add file to `vhdl-modified-file-list'. (defalias 'vhdl-add-modified-file #[0 "\203�\302 \211 \235\203� \266\202�\211 B\210\303\207" [vhdl-file-alist vhdl-modified-file-list buffer-file-name nil] 3 (#$ . 474145)])#@54 Resolve path wildcards in PATH-LIST. (fn PATH-LIST) (defalias 'vhdl-resolve-paths #[257 "\300\211\211C\300C\300\2034�@\262\301\302\"\210\303\304\305\"!\203%�\211B\262\202-�\306\307\304\305\"\"\210A\262\202�\203\251�@\262\301\310\"\203\217�\304\311\"\240\210\304\312\"\240\210\313\314\315\316#\317\304\305\"\320\321\322\304\323\n\"!P#\300\203\203�\303@!\203|�@B\262A\262\202k�\262\"A\"\262\2024�\301\324\"\210\303\304\305\"!\203\242�\211B\262A\262\2024�\237\207" [nil string-match "\\(-r \\)?\\(\\([^?*]*[/\\]\\)*\\)" file-directory-p match-string 2 vhdl-warning-when-idle "No such directory: \"%s\"" "\\(-r \\)?\\(\\([^?*]*[/\\]\\)*\\)\\([^/\\]*[?*][^/\\]*\\)\\([/\\].*\\)" 1 5 append mapcar make-closure #[257 "\301\242\300\242Q\207" [V0 V1] 4 "\n\n(fn VAR)"] vhdl-directory-files t "\\<" wildcard-to-regexp 4 "\\(-r \\)?\\(.*\\)[/\\].*"] 17 (#$ . 474369)])#@96 If UNIT is displayed in DIRECTORY, goto this line and return t, else nil. (fn DIRECTORY UNIT) (defalias 'vhdl-speedbar-goto-this-unit #[514 "`\203 �eb\210\202�\301!\203!�\302\303\304Q\305\306#\203!�\307 \210\306\207\211b\210\305\207" [vhdl-speedbar-show-projects speedbar-goto-this-file re-search-forward "[]}] " "\\>" nil t speedbar-position-cursor-on-line] 7 (#$ . 475278)])#@200 When user clicks on TEXT, load file with name and position in TOKEN. Jump to the design unit if `vhdl-speedbar-jump-to-unit' is t or if the file is already shown in a buffer. (fn TEXT TOKEN INDENT) (defalias 'vhdl-speedbar-find-file #[771 "@\204 �\302\303!\207\304@!\305@!\210\204�\211\203%�eb\210ASy\210\306 \210\307\310\211\"\210\311 !\210\312 \207" [vhdl-speedbar-jump-to-unit dframe-update-speed error "ERROR: File cannot be found" get-file-buffer speedbar-find-file-in-frame recenter vhdl-speedbar-update-current-unit t speedbar-set-timer dframe-maybee-jump-to-attached-frame] 7 (#$ . 475666)])#@71 Copy the port of the entity/component or subprogram under the cursor. (defalias 'vhdl-speedbar-port-copy #[0 "\300\301!\211\204�\300\302!\204�\303\304!\207\305 \210\306\307!\203B�\31012�\311\312\224\313\"\314@\315\316\317##\2620\207\303\320\203<�\321\202=�\322A@#\207\303\323!\207" [vhdl-speedbar-check-unit entity subprogram error "ERROR: No entity/component or subprogram under cursor" beginning-of-line looking-at "\\([0-9]\\)+:\\s-*\\(\\[[-+?]]\\|>\\) \\(\\(\\w\\|\\s_\\)+\\)" (error) get-text-property 3 speedbar-token vhdl--visit-file t make-closure #[0 "eb\210\300ASy\210\302\210\301\203�\303 \207\304 \207" [V0 V1 nil vhdl-port-copy vhdl-subprog-copy] 1] "ERROR: %s not scanned successfully\n (%s)" "Port" "Interface" "ERROR: No entity/component or subprogram on current line"] 9 (#$ . 476279) nil])#@59 Place the entity/component under the cursor as component. (defalias 'vhdl-speedbar-place-component #[0 "\302\303!\204\n�\304\305!\207\306 \210\307\310!\203�\311\312\301\313\"!\210\202!�\314!\210\315 \210\314 !\207" [speedbar-attached-frame speedbar-frame vhdl-speedbar-check-unit entity error "ERROR: No entity/component under cursor" vhdl-speedbar-port-copy fboundp speedbar-select-attached-frame dframe-select-attached-frame dframe-current-frame speedbar-mode select-frame vhdl-compose-place-component] 4 (#$ . 477107) nil])#@63 Generate configuration for the architecture under the cursor. (defalias 'vhdl-speedbar-configuration #[0 "\301\302!\204\n�\303\304!\207\305 \306 \307\310!\203�\311\312\313\314\"!\210\202\"�\315!\210\316\"\207" [speedbar-attached-frame vhdl-speedbar-check-unit architecture error "ERROR: No architecture under cursor" vhdl-speedbar-line-text vhdl-speedbar-higher-text fboundp speedbar-select-attached-frame dframe-select-attached-frame dframe-current-frame speedbar-frame speedbar-mode select-frame vhdl-compose-configuration] 6 (#$ . 477642) nil])#@50 Select the architecture under the cursor as MRA. (defalias 'vhdl-speedbar-select-mra #[0 "\303\304!\204\n�\305\306!\207\307 \227\310 \227\311\312 \206�\313 !\"\311\n\"\211AAAA\240\210\314 )\207" [vhdl-entity-alist default-directory ent-alist vhdl-speedbar-check-unit architecture error "ERROR: No architecture under cursor" vhdl-speedbar-line-text vhdl-speedbar-higher-text vhdl-aget vhdl-project-p abbreviate-file-name speedbar-refresh] 6 (#$ . 478200) nil])#@67 Make (compile) design unit or directory/project under the cursor. (defalias 'vhdl-speedbar-make-design #[0 "\212\303 \210\304\305!)\204�\306\307!\207\310\311!\312 \313 \314\315 \206�\316 !\317\320!\2031�\321\322\323\324\"!\210\2025�\325 !\210\211\326\205=�!*\207" [vhdl-project speedbar-attached-frame default-directory beginning-of-line looking-at "[0-9]+: *\\(\\(\\[\\)\\|<\\)" error "ERROR: No primary design unit or directory/project under cursor" match-string 2 vhdl-speedbar-line-text vhdl-speedbar-line-project file-name-as-directory speedbar-line-file speedbar-line-directory fboundp speedbar-select-attached-frame dframe-select-attached-frame dframe-current-frame speedbar-frame speedbar-mode select-frame vhdl-make] 8 (#$ . 478671) nil])#@59 Generate Makefile for directory/project under the cursor. (defalias 'vhdl-speedbar-generate-makefile #[0 "\302 \303\304 \206\n�\305 !\306 *\207" [default-directory vhdl-project vhdl-speedbar-line-project file-name-as-directory speedbar-line-file speedbar-line-directory vhdl-generate-makefile] 3 (#$ . 479432) nil])#@114 Check whether design unit under cursor corresponds to DESIGN-UNIT (or its expansion function). (fn DESIGN-UNIT) (defalias 'vhdl-speedbar-check-unit #[257 "\212\300 \210\211\301\267\202(�\302\303\225\304\"\305>\202)�\302\303\225\304\"\306>\202)�\302\303\225\304\"\307=\202)�\310)\207" [speedbar-position-cursor-on-line #s(hash-table size 3 test eq rehash-size 1.5 rehash-threshold 0.8125 purecopy t data (entity 10 architecture 20 subprogram 30)) get-text-property 0 face (vhdl-speedbar-entity-face vhdl-speedbar-entity-selected-face) (vhdl-speedbar-architecture-face vhdl-speedbar-architecture-selected-face) vhdl-speedbar-subprogram-face nil] 4 (#$ . 479756)])#@72 Set hierarchy display depth to DEPTH and refresh speedbar. (fn DEPTH) (defalias 'vhdl-speedbar-set-depth #[257 "\211\301 \207" [vhdl-speedbar-hierarchy-depth speedbar-refresh] 2 (#$ . 480424)]) (custom-declare-face 'vhdl-speedbar-entity-face '((((class color) (background light)) (:foreground "ForestGreen")) (((class color) (background dark)) (:foreground "PaleGreen"))) "Face used for displaying entity names." :group 'speedbar-faces) (custom-declare-face 'vhdl-speedbar-architecture-face '((((min-colors 88) (class color) (background light)) (:foreground "Blue1")) (((class color) (background light)) (:foreground "Blue")) (((class color) (background dark)) (:foreground "LightSkyBlue"))) "Face used for displaying architecture names." :group 'speedbar-faces) (custom-declare-face 'vhdl-speedbar-configuration-face '((((class color) (background light)) (:foreground "DarkGoldenrod")) (((class color) (background dark)) (:foreground "Salmon"))) "Face used for displaying configuration names." :group 'speedbar-faces) (custom-declare-face 'vhdl-speedbar-package-face '((((class color) (background light)) (:foreground "Grey50")) (((class color) (background dark)) (:foreground "Grey80"))) "Face used for displaying package names." :group 'speedbar-faces) (custom-declare-face 'vhdl-speedbar-library-face '((((class color) (background light)) (:foreground "Purple")) (((class color) (background dark)) (:foreground "Orchid1"))) "Face used for displaying library names." :group 'speedbar-faces) (custom-declare-face 'vhdl-speedbar-instantiation-face '((((class color) (background light)) (:foreground "Brown")) (((min-colors 88) (class color) (background dark)) (:foreground "Yellow1")) (((class color) (background dark)) (:foreground "Yellow"))) "Face used for displaying instantiation names." :group 'speedbar-faces) (custom-declare-face 'vhdl-speedbar-subprogram-face '((((class color) (background light)) (:foreground "Orchid4")) (((class color) (background dark)) (:foreground "BurlyWood2"))) "Face used for displaying subprogram names." :group 'speedbar-faces) (custom-declare-face 'vhdl-speedbar-entity-selected-face '((((class color) (background light)) (:foreground "ForestGreen" :underline t)) (((class color) (background dark)) (:foreground "PaleGreen" :underline t))) "Face used for displaying entity names." :group 'speedbar-faces) (custom-declare-face 'vhdl-speedbar-architecture-selected-face '((((min-colors 88) (class color) (background light)) (:foreground "Blue1" :underline t)) (((class color) (background light)) (:foreground "Blue" :underline t)) (((class color) (background dark)) (:foreground "LightSkyBlue" :underline t))) "Face used for displaying architecture names." :group 'speedbar-faces) (custom-declare-face 'vhdl-speedbar-configuration-selected-face '((((class color) (background light)) (:foreground "DarkGoldenrod" :underline t)) (((class color) (background dark)) (:foreground "Salmon" :underline t))) "Face used for displaying configuration names." :group 'speedbar-faces) (custom-declare-face 'vhdl-speedbar-package-selected-face '((((class color) (background light)) (:foreground "Grey50" :underline t)) (((class color) (background dark)) (:foreground "Grey80" :underline t))) "Face used for displaying package names." :group 'speedbar-faces) (custom-declare-face 'vhdl-speedbar-instantiation-selected-face '((((class color) (background light)) (:foreground "Brown" :underline t)) (((class color) (background dark)) (:foreground "Yellow" :underline t))) "Face used for displaying instantiation names." :group 'speedbar-faces) (byte-code "\302\303!\203/�\304 \3051%�\205 �\306\301!\205�\307 !?\205 �\310\311!0\210\202*�\210\312\313!\210\314!\266\306\301!\204=�\315\316\317\"\210\202G�\317 \210 \203G�\320 \210\302\207" [vhdl-speedbar-auto-open speedbar-frame fboundp speedbar selected-frame (error) boundp frame-live-p speedbar-frame-mode 1 vhdl-warning-when-idle "ERROR: An error occurred while opening speedbar" select-frame add-hook speedbar-load-hook vhdl-speedbar-initialize vhdl-speedbar-refresh] 3)#@44 Return the name of the components package. (defalias 'vhdl-get-components-package-name #[0 "\301 \211\203�\302@\303\304\305#\"\207A\207" [vhdl-components-package-name vhdl-project-p vhdl-replace-string subst-char-in-string 32 95] 7 (#$ . 484479)])#@51 Create entity and architecture for new component. (defalias 'vhdl-compose-new-component #[0 "\306\307\310\311 #\nA\312\232\203�\307\313\311 #\202�\314\n\"\311\211\211\211\211\315\316#\210 \317=\204Z�\314\f\306#\320\321\322 !Q\262\323!\203O�\324\325\326Q!\204O�\327\330!\210\331!\210\332 \210\333\311!\210 \203j�\334 \210`\262db\210\202p�\335 \210\336c\210\337 \210@\203\202�\340c\210\341\342 \343 \"\210\336c\210\335 \210\336c\210\344\345!\210c\210\344\346!\210A\347>\203\241�\340c\210Bj\210\344\350!\210\351B_j\210\352c\210A\353>\203\274�\340c\210Bj\210\344\354!\210\351B_j\210\352c\210A\355>\203\327�\340c\210\344\356!\210\357\360!\204\345�\344\345!\210\361\261\210\335 \210\340c\210 \362=\204\375�\340c\210\202K\211\206eb\210p\262\314C\363 Q\306#\320\321\322 !Q\262\323!\203-\324\325\326Q!\204-\327\330!\210\331!\210\332 \210\333\311!\210 \203E\334 \210db\210\202K\335 \210\336c\210\344\364!\210c\210\344\365!\210c\210\344\366!\210Bj\210\335 \210\340c\210Bj\210\367c\210Bj\210\335 \210\336c\210@\204\236\370 \204\236Bj\210\335 \210\340c\210Bj\210\371c\210Bj\210\335 \210\336c\210\344\372!\210D\203\267\373c\210\357\360!\204\264\344\364!\210c\210\336c\210Bj\210\335 \210\340c\210Bj\210\374c\210Bj\210\335 \210\336c\210\344\356!\210\357\360!\204\343\344\364!\210\361\261\210 \203\371E\312\232\204\371\375 \210\202\377\335 \210\340c\210\211\206eb\210p\262\203q\210\376 \210q\210\376 \210\315\377\201F�\201G�\n\n#\2054\201F�\201H� \"\205B\201F�\201H� \"Q\")\207" [case-fold-search vhdl-minibuffer-local-map vhdl-compose-architecture-name vhdl-compose-create-files vhdl-entity-file-name vhdl-compose-include-header t read-from-minibuffer "entity name: " nil "" "architecture name: " vhdl-replace-string message "Creating component \"%s(%s)\"..." none "." file-name-extension buffer-file-name file-exists-p y-or-n-p "File \"" "\" exists; overwrite? " error "ERROR: Creating component...aborted" find-file erase-buffer set-buffer-modified-p vhdl-template-header vhdl-comment-display-line "\n\n" vhdl-template-package-std-logic-1164 "\n" vhdl-template-standard-package vhdl-work-library vhdl-get-components-package-name vhdl-insert-keyword "ENTITY " " IS\n" (unit all) "GENERIC (\n" 2 ");\n" (unit all) "PORT (\n" (unit all) "END " vhdl-standard-p 87 ";\n\n" separate " " "ARCHITECTURE " " OF " " IS\n\n" "-- Internal signal declarations\n" vhdl-use-direct-instantiation "-- Component declarations\n" "BEGIN" " -- " "-- Component instantiations\n" vhdl-template-footer save-buffer "%s" vhdl-use-components-package vhdl-insert-empty-lines vhdl-basic-offset vhdl-architecture-file-name vhdl-self-insert-comments vhdl-file-footer format "Creating component \"%s(%s)\"...done" "\n File created: \"%s\""] 14 (#$ . 484736) nil])#@99 Place new component by pasting current port as component declaration and component instantiation. (defalias 'vhdl-compose-place-component #[0 "\204�\306\307!\207\212\310\311 p\312\313#\216\314\n!\210\315\316\317\310#\204,�\320\316\317\310#\204,�\306\321!\210\322\323!\324 \310#\325\326\327 !Qp\330\331@\"\210\f\204n�\332 \204n�\212\320\333@\334Q\317\310#)\204n�\320\335\317\"\210\336 \210\337\317x\210\340c\210 j\210\341\310!\210\320\342\317\"\210\336 \210\337\317x\210\340c\210 j\210\343\317\310\211#\210\3448\203\325�\345!\203\226�\346!\210eb\210\320\347\350Q\317\310#\204\251�\306\351\"\210\352\224b\210\212\315\353\317\310#)\203\310�\322\323!\203\310�\352\225b\210\336\354!\210\202\316�\355c\210\356u\210\357 \210\360!\210\330\361@\"\266\203)\266\202*\207" [vhdl-port-list case-fold-search vhdl-mode-ext-syntax-table vhdl-entity-file-name vhdl-use-components-package vhdl-basic-offset error "ERROR: No port has been read" t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table re-search-backward "^architecture[ \n \f]+\\w+[ \n \f]+of[ \n \f]+\\(\\w+\\)[ \n \f]+is\\>" nil re-search-forward "ERROR: No architecture found" match-string 1 vhdl-replace-string "." file-name-extension buffer-file-name message "Placing component \"%s\"..." vhdl-use-direct-instantiation "^\\s-*component\\s-+" "\\>" "^begin\\>" beginning-of-line " \n \f" "\n\n" vhdl-port-paste-component "^end\\>" vhdl-port-paste-instance 3 file-exists-p find-file "^entity[ \n \f]+" "[ \n \f]+is\\>" "ERROR: Entity not found: \"%s\"" 0 "^\\(library\\|use\\)\\|end\\>" 2 "\n" -1 vhdl-port-paste-context-clause switch-to-buffer "Placing component \"%s\"...done"] 9 (#$ . 487551) nil])#@21 Connect components. (defalias 'vhdl-compose-wire-components #[0 "\212\306\307 p\310\311#\216\312 !\210\313\314\315\306#\204$�\316\314\315\306#\204$�\317\320!\210\321\322!\323\n\306#\324\325\326 !Q\327 \316\330\315\"\316\331\315\"\332 \323 \306#\324\325\326 !Q\315\211C\315C\315\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\333\334!\210'b\210\316\335(\306#\203\366\336\322!\262$\"\336\337!\240\210!\336\340!\240\210\321\341!\206\234�\321\342!\262 \"\242\203\266�\343\f\205\253�%\306\310\344'\"#\210\202\320�\323\n#\242\306#\324\325\326 !Q\262!\343!\306\310\345&\"#\210\346\306!\210 A@\262\347 8\262\315\211\262\315\262\203\204\350 \210\351\352\306\"\203~\336\353!\262\321\322!\203\354\321\347!\"\206\317\355\321\347!'#\202@AB\262B\262\227\262\235\204:\235\203Y\356\"\262\235\203O\202TB\262\202m\235\203f\202kB\262\321\322!\204xA\262\350 \210\202\356�\357\360\315\306#\210\350 \210\351\352\306\"\203\345\336\353!\262\321\322!\203\260\354 \321\347!\"\206\264\317\361\321\347!'#\202\264@AB\262B\262\227\262\3478\226\362\232\203R\235\204\324\235\204\345\235\203\f\356\"\262\356\"\262\235\203\202B\262\202\324\235\2033\356\"\262\235\203)\202.B\262\202\324\235\204\324\235\203H\202MB\262\202\324\235\204\324\235\204j\235\203\221\356\"\262\356\"\262\235\203\207\202\214B\262\202\324\235\203\270\356\"\262\235\203\256\202\263B\262\202\324\235\204\324\235\203\315\202\322B\262\321\322!\204\337A\262\350 \210\202\207#\237\237EB\262\202w�\363)!\210\322y\210\316\364)\306#\210\327 \262\350 \210\365\366!\203\367\347!\210`|\210\202 \262\370*!\203,\371*!\210eb\210\316\372,\373Q\315\306#\204A\317\374,\"\210\316\375\315\306#\203O\321\322!\204_\376\224b\210@j\210\377c\210\201B�u\210\201C�u\210\327 \262\201D� \210\315\210`|\210\201E�\322!\210\201F�c\210\203\225\201G�c\210\347@_j\210\201H�c\210\327 \262 \327 \262\327 \262\327 \262\316\201I�\315\306#\203\265\321\322!\204\307\376\224b\210@j\210\201J�c\210\201B�u\210\201C�u\210\327 \262 \201D� \210\315\210\f`|\210\201E�\322!\210\201F�c\210\204\362\203\201G�c\210\347@_j\210\201K�c\210\327 \262\327 \262 \327 \262\f\327 \262 \327 \262\n\237\262\203[@@\262$@A@\262\347@8\262\262\n\262\262\203\315@@\227\262@\262\201L�\201M�\"\204\305\235\204\305\235\203\232\363!\210\201N�\201O�!\"\262\327 \262\235\203\220\202\225B\262\202\305\363\201N�\n\"!\210\201O�!\262\327 \262\235\203\276\202\303B\262A\262\202?U\204\371\363\201N�\n\"!\210\201G�c\210\347@_j\210\201P�$\201Q�\261\210\363!\210\203\377@@\227\262@\262\235\204\367\235\203H\363 !\210\201N�\n\201R�!\"\262\n\327 \262 \235\203>\202CB\262\202\367\235\203\204\363\201N� \"!\210\201N�\n\201R�!\"\262\n\327 \262\f\235\203z\202B\262\202\367\235\204\224\235\203\310\363\201N�\f\201N�\"\"!\210\201R�!\262\n\327 \262 \235\203\276\202\303B\262\202\367\3478\226\201S�\232\203\367\363!\210\201T�!\210\327 \262\235\203\360\202\365B\262A\262\202\371 U\2041\363\201N�\201N�\"\"!\210\201G�c\210\347@_j\210\201U�$\201Q�\261\210\363 !\210\211U\204S\363!\210\201G�c\210@j\210\201V�$\201Q�\261\210\363!\210A\262\202\363!\210\201C�u\210U\203\202\201G�c\210\347@_j\210\201W�c\210\201C�u\210\201X�c\210\363\n!\210\201C�u\210 \nU\203\256\201G�c\210\347@_j\210\201W�c\210\201C�u\210\201X�c\210A\203\334\363 !\210\201Y� \322#\210\201Y� \322#\210\363!\210\201Y�\"\210\201Z�\201[�!!\210\333\201\\�!\266\253)\266\202*\207" [case-fold-search vhdl-mode-ext-syntax-table vhdl-entity-file-name vhdl-package-file-name vhdl-use-components-package vhdl-port-list t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table re-search-backward "^architecture[ \n \f]+\\w+[ \n \f]+of[ \n \f]+\\(\\w+\\)[ \n \f]+is\\>" nil re-search-forward error "ERROR: No architecture found" match-string 1 vhdl-replace-string "." file-name-extension buffer-file-name point-marker "^begin\\>" "^end\\>" vhdl-get-components-package-name message "Wiring components..." "^[ ]*\\(\\w+\\)[ \n \f]*:[ \n \f]*\\(\\(component[ \n \f]+\\)?\\(\\w+\\)[ \n \f]+\\(--[^\n]*\n[ \n \f]*\\)*\\(\\(generic\\)\\|port\\)[ \n \f]+map\\|\\(\\(entity\\)\\|configuration\\)[ \n \f]+\\(\\(\\w+\\)\\.\\)?\\(\\w+\\)\\([ \n \f]*(\\(\\w+\\))\\)?[ \n \f]+\\(--[^\n]*\n[ \n \f]*\\)*\\(\\(generic\\)\\|port\\)[ \n \f]+map\\)[ \n \f]*(" match-string-no-properties 4 12 7 17 vhdl--visit-file #[0 "\212eb\210\301\302\300\242\303Q\304\305#\204�\306\307\300\242\"\210\310 )\207" [V0 re-search-forward "^\\s-*component[ \n \f]+" "\\>" nil t error "ERROR: Component declaration not found: \"%s\"" vhdl-port-copy] 4] #[0 "\212eb\210\301\302\300\242\303Q\304\305#\204�\306\307\300\242\"\210\310 )\207" [V0 re-search-forward "^\\s-*entity[ \n \f]+" "\\>" nil t error "ERROR: Entity declaration not found: \"%s\"" vhdl-port-copy] 4] vhdl-port-flatten 2 vhdl-forward-syntactic-ws vhdl-parse-string "\\(\\(\\w+\\)[ \n \f]*=>[ \n \f]*\\)?\\(\\w+\\),?" 3 vhdl-aget "ERROR: Formal generic \"%s\" mismatch for instance \"%s\"" delete vhdl-re-search-forward "\\<port\\s-+map[ \n \f]*(" "ERROR: Formal port \"%s\" mismatch for instance \"%s\"" "IN" vhdl-goto-marker "^\\s-*-- Internal signal declarations[ \n \f]*-*\n" looking-at "signal\\>" beginning-of-line file-exists-p find-file "^entity[ \n \f]+" "[ \n \f]+is\\>" "ERROR: Entity not found: \"%s\"" "\\(^\\s-*generic[ \n \f]*(\\)\\|^end\\>" 0 "generic ();\n\n" vhdl-basic-offset vhdl-auto-align -4 -1 forward-sexp delete-char "(\n" "\n" "-- global generics\n" "\\(^\\s-*port[ \n \f]*(\\)\\|^end\\>" "port ();\n\n" "-- global ports\n" string-match "^[0-9]+" vhdl-max-marker vhdl-compose-insert-generic "-- generics for \"" "\"\n" vhdl-compose-insert-port "OUT" vhdl-compose-insert-signal "-- ports to \"" "-- outputs of \"" ";" ")" vhdl-align-region-groups switch-to-buffer marker-buffer "Wiring components...done"] 52 (#$ . 489281) nil])#@50 Insert ENTRY as generic declaration. (fn ENTRY) (defalias 'vhdl-compose-insert-generic #[257 "\302\303_j\210@\304A@\261\210\3038\203�\305\3038\261\210\306c\210\307 \262 \2034�\3108\2034�\311\3108\312\"\210\313c\210\207" [vhdl-basic-offset vhdl-include-port-comments nil 2 " : " " := " ";" point-marker 3 vhdl-comment-insert-inline t "\n"] 5 (#$ . 495729)])#@47 Insert ENTRY as port declaration. (fn ENTRY) (defalias 'vhdl-compose-insert-port #[257 "\302\303_j\210@\304\3038\305\3068\307\261\210\310 \262 \203*�\3118\203*�\312\3118\313\"\210\314c\210\207" [vhdl-basic-offset vhdl-include-port-comments nil 2 " : " " " 3 ";" point-marker 4 vhdl-comment-insert-inline t "\n"] 8 (#$ . 496103)])#@49 Insert ENTRY as signal declaration. (fn ENTRY) (defalias 'vhdl-compose-insert-signal #[257 "j\210\302@\303\3048\305\261\210 \203�\3068\203�\307\3068\310\"\210\311c\207" [vhdl-basic-offset vhdl-include-port-comments "signal " " : " 3 ";" 4 vhdl-comment-insert-inline t "\n"] 6 (#$ . 496448)])#@105 Generate a package containing component declarations for all entities in the current project/directory. (defalias 'vhdl-compose-components-package #[0 "\306 \210\307 \310 \311\312#\313\314\315 !Q\316 \206�\317\n!\"\320\321\211\322\323\"\210\324!\2039�\325\326\327Q!\2049�\330\331!\210\332!\210\333 \210 \203R�\334\3355\336Q!\210db\210\202X�\337 \210\340c\210\341 \210\342c\210\343 \262\342c\210\337 \210\340c\210\344\345!\210c\210\344\346!\2106j\210\337 \210\342c\2106j\210\347c\2106j\210\337 \210\340c\2106j\210\343 \262\340c\210\344\350!\210\351\352!\204\252�\344\345!\210\353\261\210 \203\300�7\354\232\204\300�\355 \210\202\306�\337 \210\342c\210 \203\374�\356\357 @8\321\360#\210\211b\210\361\312!\210 A\203\346�\340c\2106j\210\343 \262b\210\362!\210\343 \262 A\211\204\312�eb\210\363 \210\322\364#*\207" [vhdl-package-file-name vhdl-entity-alist default-directory ent-alist lazy-lock-minimum-size vhdl-compose-include-header vhdl-require-hierarchy-info vhdl-project-p vhdl-get-components-package-name vhdl-replace-string t "." file-name-extension buffer-file-name vhdl-aget abbreviate-file-name 0 nil message "Generating components package \"%s\"..." file-exists-p y-or-n-p "File \"" "\" exists; overwrite? " error "ERROR: Generating components package...aborted" find-file erase-buffer vhdl-template-header "Components package (generated by Emacs VHDL Mode " ")" vhdl-comment-display-line "\n\n" vhdl-template-package-std-logic-1164 "\n" point-marker vhdl-insert-keyword "PACKAGE " " IS\n\n" "-- Component declarations\n" "END " vhdl-standard-p 87 ";\n\n" "" vhdl-template-footer vhdl--visit-file 2 #[0 "eb\210\301@8Sy\210\302\210\303 \207" [ent-alist 3 nil vhdl-port-copy] 2] vhdl-port-paste-component vhdl-port-paste-context-clause save-buffer "Generating components package \"%s\"...done\n File created: \"%s\"" vhdl-version vhdl-basic-offset vhdl-file-footer] 10 (#$ . 496755) nil])#@135 Generate block configuration for architecture. (fn ENT-NAME ARCH-NAME ENT-ALIST-ARG CONF-ALIST-ARG INST-ALIST &optional INSERT-CONF) (defalias 'vhdl-compose-configuration-architecture #[1541 "\306 \307 \310\211\211\211\211\311\312!\210 \313\261\210\n\\\262\n\203m\n@\262\3148\203e\315\262\n\3168\262\203P�@@\232\203P�A\262A\262\2029�\203i�\nZ\262j\210\311\317!\210A\262\202P�j\210\203\214�\n\\\262\311\312!\210@\313\261\210j\210A\262\202m�\311\312!\210A@\320\3148\313\261\210\3218\262\211\203\301� \204\301�\3228\314@8\232\203\272�\211@@\211A\262\202\243�\323 \" \203\346�\f\203\346�\n\\j\210\311\324!\210\325 \326\f@\261\210\327c\210\202X\323 \3228\"\262\203X\n\\j\210\311\330!\210\325 \326@\261\210\3318\2030\323\3318\3328\206\3148\"@\206'\3318@A@\262\333\334\261\210\327c\210\203X\3318\203X\n\\j\210\335@ \331\323\331\f8\227\"8%\210j\210\311\317!\210\3168\262\nA\262 \202!�\203\206\nZ\262j\210\311\317!\210A\262\202m\nZj\210 \203\227\311\317!\202\232`|*\207" [conf-alist ent-alist vhdl-basic-offset conf-key conf-entry vhdl-compose-configuration-use-subconfiguration current-indentation line-beginning-position nil vhdl-insert-keyword "FOR " "\n" 4 t 9 "END FOR;\n" " : " 7 5 vhdl-aget "USE CONFIGURATION " vhdl-work-library "." ";\n" "USE ENTITY " 3 6 "(" ")" vhdl-compose-configuration-architecture vhdl-compose-configuration-hierarchical] 24 (#$ . 498688)])#@72 Generate configuration declaration. (fn &optional ENT-NAME ARCH-NAME) (defalias 'vhdl-compose-configuration #[512 "\306 \210\307\310 \206 �\311 !\"\307\n\310 \206�\311 !\"\312\211\211\211\313\314 p\315\316#\216\317@!\210\n\204a�\212\320\321\312\313#\203\\�\322\323!\226\324\232\204\\�\325\326!\211\262\f\203\\�\325\327!\211\262 \204`�\330\331!\210)\332A\f\333 Q\"\262\326\307\326\307\f\227\"8\f\227\"8*\262\266\334\335\"\210B\203\327�\332C\313#\336\337\340 !Q\262\341!\203\254�\342\343\344Q!\204\254�\330\345!\210\346!\210\347 \210\350\312!\210D\203\316�\351\352\n\353 \354\260!\210db\210\202\354�\355 \210\356c\210\202\354�\204\354�\357\360\312\"\210\312\210\356c\210\355 \210\356c\210`\262\361\362 \312\"\210\211`U\204\376�\356c\210\363\364!\210c\210\363\365!\210c\210\363\366!\210Ej\210\367  \f \313&\210\363\370!\210\371\261\210\203M\356c\210D\203DF\372\232\204D\373 \210\202J\355 \210\374c\210\375 \210\334\376\377\201G�\"\205a\377\201H�\"P\"*\207" [vhdl-entity-alist default-directory vhdl-config-alist conf-alist ent-alist case-fold-search vhdl-require-hierarchy-info vhdl-aget vhdl-project-p abbreviate-file-name nil t syntax-table make-closure #[0 "r\300q\210\302\301!)\207" [V0 V1 set-syntax-table] 2] set-syntax-table re-search-backward "^\\(architecture\\s-+\\(\\w+\\)\\s-+of\\s-+\\(\\w+\\)\\|end\\)\\>" match-string 1 "END" match-string-no-properties 3 2 error "ERROR: Not within an architecture" vhdl-replace-string " " message "Generating configuration \"%s\"..." "." file-name-extension buffer-file-name file-exists-p y-or-n-p "File \"" "\" exists; overwrite? " "ERROR: Creating configuration...aborted" find-file erase-buffer set-buffer-modified-p vhdl-template-header "Configuration declaration for design \"" "(" ")\"" vhdl-comment-display-line "\n\n" re-search-forward "^end\\>" vhdl-template-standard-package vhdl-work-library vhdl-insert-keyword "CONFIGURATION " " OF " " IS\n" vhdl-compose-configuration-architecture "END " ";" "" vhdl-template-footer "\n" save-buffer "%s" format vhdl-mode-ext-syntax-table vhdl-compose-configuration-name vhdl-compose-configuration-create-file vhdl-configuration-file-name vhdl-compose-include-header vhdl-basic-offset vhdl-file-footer "Generating configuration \"%s\"...done" "\n File created: \"%s\""] 17 (#$ . 500185) nil])#@53 String appended to compile command after file name. (defvar vhdl-compile-post-command "" (#$ . 502540))#@99 Return the Makefile name of the current project or the current compiler if no project is defined. (defalias 'vhdl-makefile-name #[0 "\304 \"\304\n \"\305\306\3078\206�\3078B\3108\311\3128Q\"\207" [vhdl-project-alist vhdl-project vhdl-compiler-alist vhdl-compiler vhdl-aget vhdl-replace-string "\\(.*\\)\n\\(.*\\)" 8 9 "\n" 6] 8 (#$ . 502649)])#@60 Return the directory where compilation/make should be run. (defalias 'vhdl-compile-directory #[0 "\303\304\305!\"\303 \n\"\306\203�\307\310\3118B\3128\"\202�\3138!\314\315!\203+�\2020�\316\317 \"!\207" [vhdl-project-alist vhdl-compiler-alist vhdl-compiler vhdl-aget vhdl-project-p t vhdl-resolve-env-variable vhdl-replace-string "\\(.*\\)" 5 9 6 file-name-as-directory file-name-absolute-p expand-file-name vhdl-default-directory] 7 (#$ . 503005)])#@55 Remove duplicate elements from IN-LIST. (fn IN-LIST) (defalias 'vhdl-uniquify #[257 "\300\203�@\211\235\203�\202�\211B\262\262A\262\202�\207" [nil] 5 (#$ . 503469)])#@42 Set current compiler to NAME. (fn NAME) (defalias 'vhdl-set-compiler #[257 "\302\"\203�\211\303\304 \"\207\305\306\307\"!\207" [vhdl-compiler-alist vhdl-compiler assoc message "Current compiler: \"%s\"" vhdl-warning format "Unknown compiler: \"%s\""] 5 (#$ . 503654) (byte-code "\302\303\304 \305\302$)C\207" [completion-ignore-case vhdl-compiler-alist t completing-read "Compiler name: " nil] 5)])#@29 Initialize for compilation. (defalias 'vhdl-compile-init #[0 "?\205\204� \203�\304\305\n@8@ \"?\205\204�\n\306\211\203H�\305@8\262\211@\307\232\204A�\304@\"\204A�\211@A@\3108\3118FB\262A\262\202�\312 \237\"\266\n\306\211\313\262\203{�\314@8\262\211@\307\232\204t�\304@\"\204t�\211B\262A\262\202V�\312 \237\"\211\266\203\207" [vhdl-emacs-22 compilation-error-regexp-alist vhdl-compiler-alist compilation-file-regexp-alist assoc 11 nil "" 2 3 append (("^Compiling \"\\(.+\\)\"" 1)) 12] 8 (#$ . 504065)])#@30 Name of file to be compiled. (defvar vhdl-compile-file-name nil (#$ . 504602))#@105 Function called within `compile' to print out file name for compilers that do not print any file names. (defalias 'vhdl-compile-print-file-name #[0 "\301\302\261\207" [vhdl-compile-file-name "Compiling \"" "\"\n"] 3 (#$ . 504687)])#@131 Get compiler options. Returning nil means do not compile this file. (fn PROJECT COMPILER FILE-NAME &optional FILE-OPTIONS-ONLY) (defalias 'vhdl-get-compile-options #[1027 "A@\302\3038\"\211@\205�\3048\305 \306\211\203-�\307@@ \"\204-�A\262\202�\2055�@A??\205\201�\203F�\204F�\310\202\201�@A\262\311\312B\"\262\203d�\311\313B\314 Q\"\262\211\203x�\311\315B\314 \314 \260\"\262\211\206\201�\206\201�)\207" [vhdl-compiler case-fold-search vhdl-aget 4 2 vhdl-work-library nil string-match default vhdl-replace-string "\\(.*\\)" "\\(.*\\)\n\\(.*\\)" "\n" "\\(.*\\)\n\\(.*\\)\n\\(.*\\)"] 18 (#$ . 504927)])#@42 Get make options. (fn PROJECT COMPILER) (defalias 'vhdl-get-make-options #[514 "\3018\302\3038\"\211A@\304 \305\306\3018B\"\262\203)�\305\307B\310Q\"\262\206.�\207" [vhdl-compiler 3 vhdl-aget 4 vhdl-makefile-name vhdl-replace-string "\\(.*\\)" "\\(.*\\)\n\\(.*\\)" "\n"] 11 (#$ . 505573)])#@78 Compile current buffer using the VHDL compiler specified in `vhdl-compiler'. (defalias 'vhdl-compile #[0 "\306 \210\307 \"\307\n \"\206�\310\311 \"\211@\312  \203 �\313 \202$�\314\313 !\315#\316\317\f!\2047�\310\320\f\"\210\321\322\"\203D�\323\323Q\262 \203M�\313 \202Q�\314\313 !\3248A@\325U\203j�\3268A@\325U\203j�\327\211\203\213�\205\216�\330\322\322\331\232?\205\205�\322P\260!\202\216�\332\333!*\207" [vhdl-project-alist vhdl-project vhdl-compiler-alist vhdl-compiler default-directory vhdl-compile-absolute-path vhdl-compile-init vhdl-aget error "ERROR: No such compiler: \"%s\"" vhdl-compile-directory buffer-file-name file-relative-name vhdl-get-compile-options nil file-directory-p "ERROR: Compile directory does not exist: \"%s\"" string-match " " "\"" 10 0 11 vhdl-compile-print-file-name compile "" vhdl-warning "Your project settings tell me not to compile this file" compilation-process-setup-function vhdl-compile-file-name vhdl-compile-post-command] 13 (#$ . 505884) nil])#@41 Default target for `vhdl-make' command. (defvar vhdl-make-target "all" (#$ . 506908))#@191 Call make command for compilation of all updated source files (requires `Makefile'). Optional argument TARGET allows you to compile the design specified by a target. (fn &optional TARGET) (defalias 'vhdl-make #[256 "\211\206 �\306\307 #\310 \210\311\n \"\311\f \"\206�\312\313 \"\3148\315\"\316 \317!\2044�\312\320\"\210\321\322\232\203?�\323\202@�\324\324\260!)\207" [vhdl-make-target vhdl-minibuffer-local-map vhdl-project-alist vhdl-project vhdl-compiler-alist vhdl-compiler read-from-minibuffer "Target: " vhdl-compile-init vhdl-aget error "ERROR: No such compiler: \"%s\"" 2 vhdl-get-make-options vhdl-compile-directory file-directory-p "ERROR: Compile directory does not exist: \"%s\"" compile "" "make" " " default-directory] 11 (#$ . 507000) nil])#@53 List of regexps for VHDL compilers. For Emacs 22+. (defvar vhdl-error-regexp-emacs-alist (byte-code "\303\203Q� \203�\n@@\232\203J�\304\305\306\307\310@@\227#P!\311@8BB\262\312@8A@\313U\204J�\304\305\306\307\310@@\227#\314Q!\312@8BB\262A\262\202�\207" [vhdl-compiler-alist vhdl-compile-use-local-error-regexp vhdl-compiler ((vhdl-directory "^ *Compiling \"\\(.+\\)\"" 1)) make-symbol "vhdl-" subst-char-in-string 32 45 11 12 0 "-file"] 8) (#$ . 507782))#@32 Set up Emacs compile for VHDL. (defalias 'vhdl-error-regexp-add-emacs #[0 "\304\300!\205�\305\236?\205� \203�\306\307\310 \"\207" [compilation-error-regexp-alist-alist vhdl-compile-use-local-error-regexp compilation-error-regexp-alist vhdl-error-regexp-emacs-alist boundp vhdl-modelsim nil mapcar #[257 "\211@B\211 B\211\207" [compilation-error-regexp-alist compilation-error-regexp-alist-alist] 3 "\n\n(fn ITEM)"]] 3 (#$ . 508260) nil]) (byte-code "\203 �\301\302\303\"\210\301\207" [vhdl-emacs-22 add-hook compilation-mode-hook vhdl-error-regexp-add-emacs] 3)#@22 Generate `Makefile'. (defalias 'vhdl-generate-makefile #[0 "\303 \"\206 �\304\305 \"\3068\211\203$�\307 \310\311\312B\313 \314\315 Q\"!)\207\316 \207" [vhdl-compiler-alist vhdl-compiler default-directory vhdl-aget error "ERROR: No such compiler: \"%s\"" 4 vhdl-compile-directory compile vhdl-replace-string "\\(.*\\) \\(.*\\)" vhdl-makefile-name " " vhdl-work-library vhdl-generate-makefile-1] 8 (#$ . 508836) nil])#@87 Get packages from LIB-ALIST that belong to WORK-LIBRARY. (fn LIB-ALIST WORK-LIBRARY) (defalias 'vhdl-get-packages #[514 "\300\203�@@\227\227\232\203�@AB\262A\262\202�\207" [nil] 5 (#$ . 509262)])#@53 Generate Makefile for current project or directory. (defalias 'vhdl-generate-makefile-1 #[0 "\306 \203�\307 \"\204.�\310!\204.�\311!\210\202.�\312\n!\307 \"\204-�\310!\204-�\313!\210\210\312\314 !\306 \315 \206;�\"\315 \206D�\"@\315A\206O�\"B\316\315CD\"8\206^�\317\316\315CD\"8??\320@B\320A@B\320\3218B\320\3228B\320\3238B\3248\325 \227\326\327 \n\"\330 \331\211)E\331\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211F\331\211\211\211\211\211G\331\211\211\211\211\211\211\211\211\332 !\204\307�\333 \334\"\210'\204\326�\335\336\337D\211#\334\"\210\340\341 \"\210\f\262\f\203e\f@\262 \n@\262\321 8\203^H\203\377�\321 8\202\342\321\f8!\"\262\323 8E\343 8\262\315)\"\262\211@\262\211A@\262\331\262\331\262\344'#\345%Q!\"\262BB\262B\262\346\"\"\262\347\"\262\262\350\351D#\210E\203NE@\262\n @\262\352Q\262H\203\215\321\n8\202\225\342\321 8!\"\262\323\n8\262\324\n8\262\315)\"\262\211@\262\211A@\262\344&#\353\353'\260!\"\262BB\262B\262B\262B\262\203\"@\262\3548\203\3548\227!\232\203\3558\206\f\3248\262B\262B\262A\262\202\345\346\"\"\262\347\"\262\347\"\262\350\351D#\210EA\211E\204o\347\"EB\262\fA\211\204\343�@\262@\203e@@\211G@FH\203\205\321G8\202\215\342\321G8!\"\262\323G8\262\324G8\262\343G8\262\355G8\262\315)\"\262\211@\262\211A@\262C\262\344%#F\345%Q!\"\262FBB\262FB\262\211\352QBB\262\346\"\"\262\347\"\262\203B@\262\3218\262\3238\262\3248\227!\232\203:\203*B\262B\262\203:B\262B\262A\262\202\371\350\351D#\210F\331\347\"EB\262@A\211@\204p@B\262B\203\216B@\262 @\262 \331\262\321 8\203\205H\203\221\321 8\202\231\342\321\n8!\"\262\f\343 8\262\356 8\262\315) \"\262\211@\262\211A@\262\344$#\345%Q!\"\262\fBB\262\fB\262\346\"\"\262\347\"\262\262\350\351 D#\210\355 8\203s\f\357P\262H\203\355 8\202\342\355\n8!\"\262\315)\"\262\211@\262\211A@\262\344##\345%Q!\"\262BB\262B\262\fB\262\346\"\"\262\347\"\262\347\"\262\350\351D#\210\f\205}CEB\262BA\211B\204qB\315I+\"\315CD\"\3608\361\344\362\3558\206\255\3558B\"!\326#%\"p\331\211\211\211\211\211\363'!\262'\363&!\262&)\262 \203\352 @A\262\364@\365\"\240\210 A\262\202\316\364)\366\")\367\334\211#q\210\370 \210\371\372\373-!\374J\375\261\210 \203\376\f@\261\210\202!\3777\201M�\261\210\201N�D\201O�\201P�\201Q�!\201R� \375\261\210\201S�\201T�\f@\201U�\201V�\331#K\201W�\232\203\\\201W�\202b\201X�KP\375\261\210\201Y�\201Z�\n!\203w \202\201\342\326 :\".\"!\262 \201[�\201\\�.\201]�\f\375\261\2103\204\256\201^�-\201_�\201`�0\201a�\375\261\210\201b�c\210&\262&\203\353\201c�-\352)@@\201d�19\203\326\201W�\202\331\201e�\201f�.@A\261 \210&A\262'\202\267\201g�\201h�\261\210 \262'&\203\201i�\201j�.\352*@@\201k�\261\210&A\262'\202\370\375c\210 \262'\201l�\375L@\201m�\201n�\321L8\201o�\261\210\201p�\375LA@\201q�\201r�\261\210\201s�\375\321L8\201m�\201t�1\201k�:\203e\201W�\202n\201t�4\201u�Q\375\201v�6\201w�\201x�\344\201y�\3248B\201`�<\201z�\325 R\"\375\261\2103\204\256\201v�-\201{�\201x�\201|�1\201u�\261\210\201}�L@\353LA@\353\321L8\375\261\210\201~�c\210%\203w\364&@A@\365\"\262\364\201�\321(@8!\365\"\262%@@\262\315\f\"@\206\315@\"@\206\315B\"@\262\375\261\210\232\204\201\200�\261\210\201m�\201n�\321L8\261\210\203E\307@(\"\203>@\232\204>\201n�@\261\210A\262\202\"\201\201�-\352\201k�\261\210\203l\201\201�-\352@\201k�\261\210A\262\202R\375c\210%A\262&\202\307\201\202�c\210)\203\201)@\262 \201V�\f\f@\334$\262\fA@\262)\364\201�\3218!\365\"\262((\262(\203\326\201\203�-\352+@\201k�-A\203\310\201\204�\202\313\201m�\261\210(A\262)\202\253 \262)\201n� @\261\210'\203'@)\235\204 \307(@(\"\203 \201n�\201j�.\352+@\201k�\261\210'A\262(\202\343\203H\201\205�\201\206�=\203*\201\207�\202+\353@K\201W�\232\203>\201W�\202A\201\210�\375\261\210\202K\375c\210\203T3\204x(\262(\203t\201\211�-\352+@\201z�\261\210(A\262)\202X \262))A\211)\204\201\201\212�+\201\213�\261\210\201\214�\201\215�!\210\340\201\216�,\"\210\201\217�!\203\314\201\220� \210\201\221�p!\210q\210\201\222�\201\223�!\205\337\201\223�\201\224� \"\266\214\202\341\201\225�\336\201\226�\312 !\"!\210\201\227�p!\266\214.\207" [vhdl-project vhdl-file-alist default-directory vhdl-entity-alist ent-alist vhdl-config-alist vhdl-project-p assoc vhdl-load-cache vhdl-scan-project-contents abbreviate-file-name vhdl-scan-directory-contents vhdl-default-directory vhdl-aget 12 ("\\1.vhd" "\\2_\\1.vhd" "\\1.vhd" "\\1.vhd" "\\1_body.vhd" identity) "\\(.*\\) \\(.*\\) \\(.*\\)" 2 3 4 5 vhdl-work-library expand-file-name vhdl-compile-directory vhdl-makefile-name nil file-exists-p make-directory t vhdl-warning format "No unit-to-file name mapping found for compiler \"%s\".\n Directory of dummy files is created instead (to be used as dependencies).\n Please contact the VHDL Mode maintainer for full support of \"%s\"" message "Generating makefile \"%s\"..." file-relative-name 6 vhdl-replace-string " " vhdl-get-packages append vhdl-aput rule-alist "-" " " 8 7 10 "-body" 9 vhdl-resolve-env-variable "\\(.*\\)" vhdl-sort-alist sort string< #[514 "A@@A@@\231\207" [] 4 "\n\n(fn A B)"] find-file-noselect erase-buffer "# -*- Makefile -*-\n" "### " file-name-nondirectory " - VHDL Makefile generated by Emacs VHDL Mode " "\n" "\n# Project : " "\n# Directory : \"" conf-alist vhdl-package-alist pack-alist vhdl-compiler-alist vhdl-compiler arch-alist conf-key conf-entry vhdl-compile-absolute-path vhdl-project-alist vhdl-version vhdl-compile-post-command vhdl-makefile-default-targets "\"" "\n# Platform : " "\n# Generated : " format-time-string "%Y-%m-%d %T " user-login-name "\n\n# Define compilation command and options\n" "\nCOMPILE = " "\nOPTIONS = " vhdl-get-compile-options "" "\nPOST-COMPILE = " directory-file-name file-name-absolute-p "\n\n# Define library paths\n" "\nLIBRARY-" " = " "LIBRARY-" "-make = " "$(LIBRARY-" ")/make" "\n\n# Define library unit files\n" "\nUNIT-" " = \\\n $(LIBRARY-" "-make" ")/" "\n\n\n# Define list of all library unit files\n" "\nALL_UNITS =" " \\\n " "$(UNIT-" ")" "\n\n\n# Rule for compiling entire design\n" " :" " \\\n " " \\\n $(ALL_UNITS)\n" "\n\n# Rule for cleaning entire design\n" " : " "\n -rm -f $(ALL_UNITS)\n" "\n\n# Rule for creating library directory\n" " \\\n $(LIBRARY-" "-make)\n" "\n$(LIBRARY-" ") :" "\n " "\\(.*\\)\n\\(.*\\)" ")\n" "-make) :" "mkdir -p $(LIBRARY-" "\n\n.PHONY : " "\n\n# Rules for compiling single library units and their subhierarchy\n" vhdl-uniquify " \\\n" " \\\n $(UNIT-" "\n\n# Rules for compiling single library unit files\n" "\n$(UNIT-" " \\" "\n $(COMPILE) " default "$(OPTIONS)" " $(POST-COMPILE)" " @touch $(UNIT-" "\n\n### " " ends here\n" run-hooks vhdl-makefile-generation-hook "Generating makefile \"%s\"...done" file-writable-p save-buffer kill-buffer fboundp add-to-history file-name-history vhdl-warning-when-idle "File not writable: \"%s\"" switch-to-buffer] 75 (#$ . 509475)])#@36 Address for VHDL Mode bug reports. (defconst vhdl-mode-help-address "Reto Zimmermann <reto@gnu.org>" (#$ . 516922))#@44 Submit via mail a bug report on VHDL Mode. (defalias 'vhdl-submit-bug-report #[0 "\303\304!\205\305\306 \307\nP\310\311\312\313\314\315\316\317\320\321\322\323\324\325\326\327\330\331\332\333\334\335\336\337\340\341\342\343\344\345\346\347\350\351\352\353\354\355\356\357\360\361\362\363\364\365\366\367\370\371\372\373\374\375\376\377\201@�\201A�\201B�\201C�\201D�\201E�\201F�\201G�\201H�\201I�\201J�\201K�\201L�\201M�\201N�\201O�\201P�\201Q�\201R�\201S�\201T�\201U�\201V�\201W�\201X�\201Y�\201Z�\201[�\201\\�\201]�\201^�\201_�\201`�\201a�\201b�\201c�\201d�\201e�\201f�\201g�\201h�\201i�\201j�\201k�\201l�\201m�\201n�\201o�\201p�\201q�\201r�\201s�\201t�\201u�\201v�\201w�\201x�\201y�\201z�\201{�\201|�\201}�\201~�\201�\201\200�\201\201�\201\202�\257{\201\203�\201\204�\201\205�&)\207" [reporter-prompt-for-summary-p vhdl-mode-help-address vhdl-version y-or-n-p "Do you want to submit a report on VHDL Mode? " t reporter-submit-bug-report "VHDL Mode " vhdl-offsets-alist vhdl-comment-only-line-offset tab-width vhdl-electric-mode vhdl-stutter-mode vhdl-indent-tabs-mode vhdl-project-alist vhdl-project vhdl-project-file-name vhdl-project-autoload vhdl-project-sort vhdl-compiler-alist vhdl-compiler vhdl-compile-use-local-error-regexp vhdl-makefile-default-targets vhdl-makefile-generation-hook vhdl-default-library vhdl-standard vhdl-basic-offset vhdl-upper-case-keywords vhdl-upper-case-types vhdl-upper-case-attributes vhdl-upper-case-enum-values vhdl-upper-case-constants vhdl-use-direct-instantiation vhdl-array-index-record-field-in-sensitivity-list vhdl-compose-configuration-name vhdl-entity-file-name vhdl-architecture-file-name vhdl-configuration-file-name vhdl-package-file-name vhdl-file-name-case vhdl-electric-keywords vhdl-optional-labels vhdl-insert-empty-lines vhdl-argument-list-indent vhdl-association-list-with-formals vhdl-conditions-in-parenthesis vhdl-sensitivity-list-all vhdl-zero-string vhdl-one-string vhdl-file-header vhdl-file-footer vhdl-company-name vhdl-copyright-string vhdl-platform-spec vhdl-date-format vhdl-modify-date-prefix-string vhdl-modify-date-on-saving vhdl-reset-kind vhdl-reset-active-high vhdl-clock-rising-edge vhdl-clock-edge-condition vhdl-clock-name vhdl-reset-name vhdl-model-alist vhdl-include-port-comments vhdl-include-direction-comments vhdl-include-type-comments vhdl-include-group-comments vhdl-actual-generic-name vhdl-actual-port-name vhdl-instance-name vhdl-testbench-entity-name vhdl-testbench-architecture-name vhdl-testbench-configuration-name vhdl-testbench-dut-name vhdl-testbench-include-header vhdl-testbench-declarations vhdl-testbench-statements vhdl-testbench-initialize-signals vhdl-testbench-include-library vhdl-testbench-include-configuration vhdl-testbench-create-files vhdl-testbench-entity-file-name vhdl-testbench-architecture-file-name vhdl-compose-create-files vhdl-compose-configuration-create-file vhdl-compose-configuration-hierarchical vhdl-compose-configuration-use-subconfiguration vhdl-compose-include-header vhdl-compose-architecture-name vhdl-components-package-name vhdl-use-components-package vhdl-self-insert-comments vhdl-prompt-for-comments vhdl-inline-comment-column vhdl-end-comment-column vhdl-auto-align vhdl-align-groups vhdl-align-group-separate vhdl-align-same-indent vhdl-highlight-keywords vhdl-highlight-names vhdl-highlight-special-words vhdl-highlight-forbidden-words vhdl-highlight-verilog-keywords vhdl-highlight-translate-off vhdl-highlight-case-sensitive vhdl-special-syntax-alist vhdl-forbidden-words vhdl-forbidden-syntax vhdl-directive-keywords vhdl-speedbar-auto-open vhdl-speedbar-display-mode vhdl-speedbar-scan-limit vhdl-speedbar-jump-to-unit vhdl-speedbar-update-on-saving vhdl-speedbar-save-cache vhdl-speedbar-cache-file-name vhdl-index-menu vhdl-source-file-menu vhdl-hideshow-menu vhdl-hide-all-init vhdl-print-two-column vhdl-print-customize-faces vhdl-intelligent-tab vhdl-indent-syntax-based vhdl-indent-comment-like-next-code-line vhdl-word-completion-case-sensitive vhdl-word-completion-in-minibuffer vhdl-underscore-is-part-of-word vhdl-mode-hook #[0 "\203�\301\302\303\"\304Q\202�\305c\207" [vhdl-special-indent-hook "\n@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\nvhdl-special-indent-hook is set to '" format "%s" ".\nPerhaps this is your problem?\n@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n\n" "\n"] 4] nil "Hi Reto,"] 126 (#$ . 517043) nil])#@2144 Release Notes for VHDL Mode 3.37 ================================ - Added support for VHDL'08: - New keywords, types, functions, attributes, operators, packages - Context declaration - Block comments - Directives - `all' keyword in sensitivity list Release Notes for VHDL Mode 3.34 ================================ - Added support for GNU Emacs 22/23/24: - Compilation error parsing fixed for new `compile.el' package. - Port translation: Derive actual generic name from formal generic name. - New user options: `vhdl-actual-generic-name': Specify how actual generic names are obtained. Release Notes for VHDL Mode 3.33 ================================ New Features ------------ CONFIGURATION DECLARATION GENERATION: - Automatic generation of a configuration declaration for a design. (See documentation (`C-c C-h') in section on STRUCTURAL COMPOSITION.) Key Bindings ------------ For Emacs compliance the following key bindings have been changed: - `C-c c' -> `C-c C-c' `vhdl-comment-uncomment-region' - `C-c f' -> `C-c C-i C-f' `vhdl-fontify-buffer' - `C-c s' -> `C-c C-i C-s' `vhdl-statistics-buffer' - `C-c C-c ...' -> `C-c C-m ...' `vhdl-compose-...' User Options ------------ `vhdl-configuration-file-name': (new) Specify how the configuration file name is obtained. `vhdl-compose-configuration-name': (new) Specify how the configuration name is obtained. `vhdl-compose-configuration-create-file': (new) Specify whether a new file should be created for a configuration. `vhdl-compose-configuration-hierarchical': (new) Specify whether hierarchical configurations should be created. `vhdl-compose-configuration-use-subconfiguration': (new) Specify whether subconfigurations should be used inside configurations. `vhdl-makefile-default-targets': (new) Customize names of Makefile default targets. `vhdl-indent-comment-like-next-code-line': (new) Specify whether comment lines are indented like following code line. `vhdl-array-index-record-field-in-sensitivity-list': (new) Specify whether to include array indices / record fields in sensitivity list. (defconst vhdl-doc-release-notes nil (#$ . 521418))#@1383 Reserved words in VHDL ---------------------- VHDL'08 (IEEE Std 1076-2008): `vhdl-08-keywords' : keywords `vhdl-08-types' : standardized types `vhdl-08-attributes' : standardized attributes `vhdl-08-functions' : standardized functions `vhdl-08-packages' : standardized packages and libraries VHDL'93/02 (IEEE Std 1076-1993/2002): `vhdl-02-keywords' : keywords `vhdl-02-types' : standardized types `vhdl-02-attributes' : standardized attributes `vhdl-02-enum-values' : standardized enumeration values `vhdl-02-functions' : standardized functions `vhdl-02-packages' : standardized packages and libraries VHDL-AMS (IEEE Std 1076.1 / 1076.1.1): `vhdl-ams-keywords' : keywords `vhdl-ams-types' : standardized types `vhdl-ams-attributes' : standardized attributes `vhdl-ams-enum-values' : standardized enumeration values `vhdl-ams-constants' : standardized constants `vhdl-ams-functions' : standardized functions Math Packages (IEEE Std 1076.2): `vhdl-math-types' : standardized types `vhdl-math-constants' : standardized constants `vhdl-math-functions' : standardized functions `vhdl-math-packages' : standardized packages Forbidden words: `vhdl-verilog-keywords' : Verilog reserved words NOTE: click `mouse-2' on variable names above (not in XEmacs). (defconst vhdl-doc-keywords nil (#$ . 523620))#@660 For VHDL coding style and naming convention guidelines, see the following references: [1] Ben Cohen. "VHDL Coding Styles and Methodologies". Kluwer Academic Publishers, 1999. http://members.aol.com/vhdlcohen/vhdl/ [2] Michael Keating and Pierre Bricaud. "Reuse Methodology Manual, Second Edition". Kluwer Academic Publishers, 1999. http://www.openmore.com/openmore/rmm2.html [3] European Space Agency. "VHDL Modelling Guidelines". https://amstel.estec.esa.int/tecedm/website/docs_generic/ModelGuide.pdf Use user options `vhdl-highlight-special-words' and `vhdl-special-syntax-alist' to visually support naming conventions. (defconst vhdl-doc-coding-style nil (#$ . 525055))#@58 Echo the current version of VHDL Mode in the minibuffer. (defalias 'vhdl-version #[0 "\302\303 #\210\304 \207" [vhdl-version vhdl-time-stamp message "VHDL Mode %s (%s)" vhdl-keep-region-active] 4 (#$ . 525770) nil])#@67 Display VARIABLE's documentation in *Help* buffer. (fn VARIABLE) (defalias 'vhdl-doc-variable #[257 "\306\307D\310\311!\"\210r\312\313\314!\203�\314 \202�\315!q\210p\316 \210\317\211\320\211\320\321 \210\322\323!+\210\211\324\325\326\"!\210rq\210\327 )\210\330 \331!)\210\207" [default-directory buffer-read-only buffer-file-name buffer-undo-list inhibit-modification-hooks inhibit-read-only help-setup-xref vhdl-doc-variable called-interactively-p interactive get-buffer-create fboundp help-buffer "*Help*" kill-all-local-variables nil t erase-buffer run-hooks temp-buffer-setup-hook princ documentation-property variable-documentation help-mode help-print-return-message internal-temp-output-buffer-show standard-output] 8 (#$ . 525992) nil])#@51 Display VHDL Mode documentation in *Help* buffer. (defalias 'vhdl-doc-mode #[0 "\306\307C\310\311!\"\210r\312\313\314!\203�\314 \202�\315!q\210p\316 \210\317\211\320\211\320\321 \210\322\323!+\210\211\324!\210\324\325!\210\324\326\327!!\210rq\210\330 )\210\331 \332!)\210\207" [default-directory buffer-read-only buffer-file-name buffer-undo-list inhibit-modification-hooks inhibit-read-only help-setup-xref vhdl-doc-mode called-interactively-p interactive get-buffer-create fboundp help-buffer "*Help*" kill-all-local-variables nil t erase-buffer run-hooks temp-buffer-setup-hook princ " mode:\n" documentation vhdl-mode help-mode help-print-return-message internal-temp-output-buffer-show standard-output mode-name] 6 (#$ . 526760) nil]) (provide 'vhdl-mode)